high-speed interface

A Charged Device Model (CDM) simulation method has been demonstrated to predict CDM fail current of receiving circuits with gate oxide connected to pad. This method involves inclusion of 20ps rise time edge into the stimulus. It was shown previously that this fast rise time component of the pulse can cause the gate oxide damage. The simulation method is intended as a schematic-level tool during pre-silicon design phase to deliver CDM ESD protection. Simulation results are verified by silicon results with qualification CDM test on package and Transmission-Line-Pulse (TLP) measurements on wafer-level.

It is no trivial matter to properly interpret system level test results on high-speed boards. Board manufacturers (OEMs) assess the ESD robustness of their system by means of gun testing, not always in accordance with the IEC standard.

Learn about the design of a stand-alone (off- chip) protection device which meets all requirements.