Hans Kunz

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.

It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).

There is often confusion about the interaction between IC-level component ESD protection and the appropriately required system-level ESD protection strategy.

How is the proper ESD Protection Cell chosen for a particular design application?

Robust ESD protection does not ensure that IC designs are protected from unintended EOS effects. This article identifies areas of risk in some ESD design methods.