Get our free email newsletter

FinFET

ESD Co-Design for High-Speed SerDes in FinFET Technologies

The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.

Next to FinFET, How Will ESD Suffer?

Several new transistor architectures have been proposed to achieve more powerful computing capability. In this article, we will look at the impacts of these transistor architectures on ESD reliability.

FinFETs and Their Impact on ESD Protection Design

This article reviews some of the ESD protection design challenges when designing in a FinFET technology and give an outlook on the successors of FinFET.

Digital Sponsors

Become a Sponsor

Discover new products, review technical whitepapers, read the latest compliance news, trending engineering news, and weekly recall alerts.

Get our email updates

What's New

- From Our Sponsors -

Sign up for the In Compliance Email Newsletter

Discover new products, review technical whitepapers, read the latest compliance news, trending engineering news, and weekly recall alerts.