esd

The electronic industry has embraced simulation to address several complex design challenges, but reliability is still mostly dealt with best design practices and tested with prototypes. In this article, we present how modeling and simulation approaches can help designers perform virtual prototyping and uncover reliability issues especially EOS/ESD before going for physical prototypes.

How is the proper ESD Protection Cell chosen for a particular design application?

The purpose of AMR is to warn “customers” who use the semiconductor product that there are physical limits that must not be violated if reliability is to be preserved.

This article reviews some of the ESD protection design challenges when designing in a FinFET technology and give an outlook on the successors of FinFET.

CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.

Cable discharge events occur more frequently than we think, but they often go unrecognized or undiagnosed for root causes, resulting in unnecessary device failures. This article discusses the origins of three types of cable discharge events.

Confusion over ESD flooring resistance terminology and requirements abounds, leaving many in the dark and creating potential risks. This article helps to clarify this complicated issue so that you can work to mitigate the problem.

Optical communication can dramatically increase the bandwidth between servers while reducing complexity, power consumption, and cost.

Single electromagnetic pulses like lightning, ESD, powerline transients, NEMP, etc., are generally described in time domain, while filters and shields are practically always characterized in frequency domain. This article describes a quick and handy formula and nomogram providing a fair estimate of the filter or shield response to a conducted or radiated threat.

Robust ESD protection does not ensure that IC designs are protected from unintended EOS effects. This article identifies areas of risk in some ESD design methods.