esd

Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable.

During the last four decades, damage to devices from electrical overstress (EOS) has confounded both IC suppliers and customers. The Industry Council on ESD Target Levels investigated numerous EOS root causes and established a white paper on the subject, JEP174 [1].

In this article we discuss the MOS transistor in the role of ESD protection for high-voltage applications and take a look into a possible future of ESD protection devices for high-performance computing applications.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.

It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).

2.5D/3D integration is an Integrated Circuit (IC) packaging technique that allows the combination of dies of the same or different technologies in the same IC package.

This article explores the waveform specifications called out in the IEC 61000-4-2 standard.

To provide in-depth coverage of ESD testing methods, in this article, we look at another type of ESD testing based on the “Human Body Model” (HBM) method of ESD testing.

Nowadays in the semiconductors industry, the bipolar transistor is massively used for various functions in modern integrated circuits (ICs) products.

Ethernet solutions have been popular in industrial and computing applications for several decades but were not widely adopted in the automotive area. Automotive ethernet enables fast and robust data communication, with high flexibility in bus topologies for multiple electronic control units (ECUs).