esd

This column outlines the steps to consider when embedding ESD detection capabilities into your system and overall design flow.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.

This column focuses on the practical aspects of implementing embedded ESD detection. We’ll provide a step-by-step guide, discuss validation and testing methodologies, present case studies, and delve into future trends and innovations in the field.

The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.

ESD “event detectors” have been used for years in factory environments to identify and remediate ESD discharges during manufacturing. Now design engineers are embedding system-level and on-chip ESD detection technologies into their systems to analyze and recover from both factory and field ESD events.

This article describes a practical way to improve signal integrity of typical interfaces on the PCB when using external ESD devices.

In this article, we describe how wireless measurements of human body voltage can be made, and why they are important for ESD managers.

Simple star-tree networks, as shown here for USB2, should have wide applicability for cables carrying fast signals.

This updated version of an article originally published in the March 2014 issue provides details on recent and current developments in the ESD testing of electronic products.

In Part 1 of the article, we reviewed what EDA tools are good for. Here we will discuss EDA tool limitations.