esd

The electronics industry is continually shifting. Device density and technology is more complex. Electronics manufacturing is more heavily reliant on out‑sourcing. The ESD industry seems to have jumped into this swirling eddy headfirst. ESD control programs have mushroomed. Black has been replaced by green, blue and gold. Shielding bags dominate the warehouse. Ionizers exist along side wrist straps and ground cords. An early history of “smoke and mirrors,” magic and lofty claims of performance is rapidly and safely being relegated to the past.

Your static control program is up and running. How do you determine whether it is effective? How do you make sure your employees follow it? In Part 3, we suggested that there were at least nine critical elements to successfully developing and implementing an effective ESD control program. In Part 4, we will focus on two more of these elements: training and auditing.

Many sources recently have reported that electrical failures to components previously classified as EOS (Electrical Overstress) are instead the result of ESD (Electrostatic Discharge) failures due to charged-board events (CBE) [1,2]. A charged printed circuit board assembly stores substantially more charge than a discrete device as its capacitance is larger. A subsequent discharge of the board assembly results in increased current for that event - versus that of the discrete component. Consequently, a device’s CDM (charged device model) rating is lowered when mounted in a printed circuit board (PCB). In an attempt to get a feel for just how much it is lowered, we conducted CDM stress tests on components in discrete form, and again after insertion into larger and larger sized pc boards. We found that the CDM ratings are lowered dramatically!

The electronics industry is terribly confused by the term Class 0. Particularly when it comes to electrostatic discharge (ESD) device sensitivity and how the term applies to factory controls designed to mitigate ESD. The confusion manifests itself through the many companies and engineers seeking direction on how to “become qualified to handle Class 0 devices.” They are seeking this information because their equally confused customers have imposed requirements on them to meet this mythical level of performance. Not only is Class 0 as a factory level of performance a contrived ideal, it is not a realistic or useful goal. Our purpose here is to explain reality and what is necessary for understanding device ESD sensitivity and establishing control.

Integrated circuits are tested for their robustness to electrostatic discharge (ESD) using the Human Body Model (HBM) and Charged Device Model (CDM) test methods. Circuits which pass 1000 V HBM or 250 to 500 V CDM can be handled with high yield in manufacturing facilities using basic ESD control procedures. [1, 2] HBM is the oldest, best known and most widely used ESD test method, but most ESD factory control experts contend that the vast majority of ESD failures in modern manufacturing lines are better represented by the CDM test method. The CDM test method is intended to reproduce what happens when an integrated circuit becomes charged during handling, and then discharges to a grounded surface.

Anyone who has worked in Quality or Reliability in a large corporation knows that developing and presenting credible failure cost information can be difficult. This is particularly true for ESD, where the events are invisible and not nearly as well understood as other more obvious classes of failure, such as mechanical or contamination. The “real” cost of ESD can be a hot topic of discussion each year when program budgets are being developed for manufacturing and R&D programs. The challenge is that every year there are new high-level people in the financial and planning organizations who are not technical experts and who are asking hard questions about the justification for the ESD investment. In years when revenue is down, the questions become more difficult and better evidence is often demanded. The author was directly involved in this process for 15 years, starting in 1986. At the time the following quote was a part of many ESD funding discussions; “… in the electronics industry, losses associated with ESD are estimated at between a half billion and five billion dollars annually.” The exact original reference for this assertion has been lost, at least to this author. Nonetheless it was used many times over the next few years in presentations to the corporate check writers. Furthermore, during research for background information for this article, the exact same quote appeared (unattributed) in an article from 1992 [1] and in a book published in 2006 [2]. Needless to say, a well-stated assertion of value can go a long way – at least in trade literature. However, this author can also report that the usefulness of this, inside the corporation, eroded much faster. By 1990, a well-known director in Bell Labs said; “… that was then… I think this problem has been solved!” Many of us would scoff at such a declaration, knowing full well that ESD problems were continuing to occur. However, the directors’ challenge was an appropriate one. His experience came from the semiconductor process world where he had seen significant ESD sources eliminated and device thresholds (albeit HBM only) steadily increase. Corporations would like their investments to be justified by more timely and relevant data and observations.  They ask, “What is the “real” cost?”

With the destabilization of the economy, many companies are looking for ways to increase profits and performance within their particular industry. The electronics industry is no exception. Many electronics companies are working towards improved quality and reliability at the same rate as improving the performance of the products they manufacture.