esd

ESD “event detectors” have been used for years in factory environments to identify and remediate ESD discharges during manufacturing. Now design engineers are embedding system-level and on-chip ESD detection technologies into their systems to analyze and recover from both factory and field ESD events.

This article describes a practical way to improve signal integrity of typical interfaces on the PCB when using external ESD devices.

In this article, we describe how wireless measurements of human body voltage can be made, and why they are important for ESD managers.

Simple star-tree networks, as shown here for USB2, should have wide applicability for cables carrying fast signals.

This updated version of an article originally published in the March 2014 issue provides details on recent and current developments in the ESD testing of electronic products.

In Part 1 of the article, we reviewed what EDA tools are good for. Here we will discuss EDA tool limitations.

Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable.

During the last four decades, damage to devices from electrical overstress (EOS) has confounded both IC suppliers and customers. The Industry Council on ESD Target Levels investigated numerous EOS root causes and established a white paper on the subject, JEP174 [1].

In this article we discuss the MOS transistor in the role of ESD protection for high-voltage applications and take a look into a possible future of ESD protection devices for high-performance computing applications.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.