Local PCB Layout Tweaks for Improved Signal Integrity When Using ESD Protection Devices
This article describes a practical way to improve signal integrity of typical interfaces on the PCB when using external ESD devices.
Is Wireless Measurement of Human Body Voltage Possible?
In this article, we describe how wireless measurements of human body voltage can be made, and why they are important for ESD managers.
CDE Modeling Using Star-Tree Impedance Networks for USB2 Cable
Simple star-tree networks, as shown here for USB2, should have wide applicability for cables carrying fast signals.
A Brief History of Electrostatic Discharge (ESD) Testing of Electronic Products
This updated version of an article originally published in the March 2014 issue provides details on recent and current developments in the ESD testing of electronic products.
Can Electrostatic Discharge Design Problems Be Solved with Electronic Design Automation Tools Alone? Part 2
In Part 1 of the article, we reviewed what EDA tools are good for. Here we will discuss EDA tool limitations.
Can Electrostatic Discharge Design Problems Be Solved with Electronic Design Automation Tools Alone? Part 1
Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable.
The Dilemma Between Customers and Suppliers on EOS Failures
During the last four decades, damage to devices from electrical overstress (EOS) has confounded both IC suppliers and customers. The Industry Council on ESD Target Levels investigated numerous EOS root causes and established a white paper on the subject, JEP174 [1].
The Transistor: An Indispensable ESD Protection Device – Part 2
In this article we discuss the MOS transistor in the role of ESD protection for high-voltage applications and take a look into a possible future of ESD protection devices for high-performance computing applications.
ESD Designers’ Headache with Multiple Automotive Test Requirements, Part I
The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer. Implications of EMC-ESD immunity co-design will be reviewed along with several case studies.
Challenges of Designing System-level ESD Protection at the IC Level, Part 2
It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).