Low Voltage Charged Device Model (CDM) Testing at a Crossroads

Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.

What Are External Latch-up and Internal Latch-up?

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

Use of HBM and CDM Layout Simulation Tools

The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.

Ohm’s Law Also Applies to ESD‑Induced Heat Pulses

Heat flow analysis for semiconductor ESD situations can be approximated to one dimension, and then captured with a generalized Ohm’s Law using a complex impedance. Methods can include time-dependent electrothermal pulses and feedback due to self-heating, with solutions readily carried out on any desktop computer.

What Are the Advantages of Capacitively Coupled TLP (CC-TLP)?

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.

Static Control Flooring in High Reliability Environments

High reliability organizations (HROs) typically implement stringent static control programs to mitigate the risks of catastrophic and/or life-threatening failures. This article describes some of the considerations to consider for static control flooring in these more demanding environments.