ESD Challenges in 2.5D/3D Integration
2.5D/3D integration is an Integrated Circuit (IC) packaging technique that allows the combination of dies of the same or different technologies in the same IC package.
The Transistor: An Indispensable ESD Protection Device – Part 1
Nowadays in the semiconductors industry, the bipolar transistor is massively used for various functions in modern integrated circuits (ICs) products.
The Many Aspects of Semiconductor Reliability with Impact on ESD Design
Reliability issues need to be continuously addressed during technology development as technologies further advance into novel transistor structures such as FinFETs and Multi-gate devices.
Commercial Versus Automotive ESD Integrated Circuit Qualification: Part 2
This is Part 2 of an article describing the difference between the electrostatic discharge (ESD) qualification requirements for automotive and standard commercial integrated circuits.
Commercial Versus Automotive ESD Integrated Circuit Qualification, Part 1
Integrated circuits intended for automotive applications have higher electrostatic discharge (ESD) qualification requirements than those intended for commercial and consumer electronics.
Industry Council’s Latch‑up Survey
This article provides a high-level overview of the Industry Council paper “Survey on Latch‑up Testing Practices and Recommendations for Improvements,” which describes the full analysis of the collected responses and lays a path for potential adaptations needed to accommodate its use in future technologies and applications.
Challenges of Designing System-Level ESD Protection at the IC-Level
There is often confusion about the interaction between IC-level component ESD protection and the appropriately required system-level ESD protection strategy.
Latch-up Electronic Design Automation Checks
This article introduces typical latch-up verification techniques to detect and prevent latch-up. These techniques rely on electronic design automation (EDA) tools to deliver the coverage necessary to identify and eliminate latch-up risks.
Characterization for ESD Design, the TLP Zoo: Part 1
Author’s Note: This is the first of a two-part series on the TLP Zoo, the variety of transmission line pulse (TLP) systems used in the characterization of electrical components and system of ESD robustness. In ... Read More...
Use of HBM and CDM Layout Simulation Tools
The methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.