Indium-gallium-zinc-oxide (IGZO) Thin-film-transistors (TFT) and ESD
The thin-film transistor (TFT) became commercially available slightly more than 30 years ago in the form of a switch for the Liquid Crystal Display.
Characterization for ESD Design, the TLP Zoo: Part 2
This is the second of a two-part series on transmission line pulse (TLP) testing.
What Are External Latch-up and Internal Latch-up?
Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product.
Understanding Footwear and Flooring in ESD Control
If you really want to know whether your footwear and flooring are working together, measure the resistance from the wearer via footwear and flooring to earth (ground).
Controlling Static Electricity: A 50-Year History
Our knowledge of ESD and how to control it has grown significantly over the past 50 years. This article maps the history of that journey.
System-Level Simulation Solutions for EOS and ESD
The electronic industry has embraced simulation to address several complex design challenges, but reliability is still mostly dealt with best design practices and tested with prototypes. In this article, we present how modeling and simulation approaches can help designers perform virtual prototyping and uncover reliability issues especially EOS/ESD before going for physical prototypes.
Next Generation Charged Device Model ESD Testing
The charged device model describes the electrostatic discharge (ESD) event that occurs when an integrated circuit (IC) is rapidly charged or discharged through a single pin to a metallic surface.