EOS/ESD Association

The ESDA technology roadmap is written to support and guide the daily work of ESD and latch-up experts in the worldwide industry and academia.

In Part 1 of the article, we reviewed what EDA tools are good for. Here we will discuss EDA tool limitations.

Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable.

In this article we discuss the MOS transistor in the role of ESD protection for high-voltage applications and take a look into a possible future of ESD protection devices for high-performance computing applications.

As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.

It is a common misconception that designing an IC for system-level ESD requirements simply requires an increase in the capability of the ESD cells, which are already present for safe handling ESD requirements, like Human Body Model (HBM).

2.5D/3D integration is an Integrated Circuit (IC) packaging technique that allows the combination of dies of the same or different technologies in the same IC package.

Nowadays in the semiconductors industry, the bipolar transistor is massively used for various functions in modern integrated circuits (ICs) products.

Reliability issues need to be continuously addressed during technology development as technologies further advance into novel transistor structures such as FinFETs and Multi-gate devices.

This is Part 2 of an article describing the difference between the electrostatic discharge (ESD) qualification requirements for automotive and standard commercial integrated circuits.