design

This series of articles delves into the design principles of power filters for switched-mode power converters and similar applications, focusing on conducted and radiated emissions. Part 1 provides an overview of filter design principles, emphasizing the need for specialized approaches to meet EMC specifications in an increasingly electrified and sustainable world.

A Charged Device Model (CDM) simulation method has been demonstrated to predict CDM fail current of receiving circuits with gate oxide connected to pad. This method involves inclusion of 20ps rise time edge into the stimulus. It was shown previously that this fast rise time component of the pulse can cause the gate oxide damage. The simulation method is intended as a schematic-level tool during pre-silicon design phase to deliver CDM ESD protection. Simulation results are verified by silicon results with qualification CDM test on package and Transmission-Line-Pulse (TLP) measurements on wafer-level.

This article provides an overview of high-altitude electromagnetic pulses and the damaging effects they pose to sensitive electronic circuitry, equipment and systems that support a wide range of critical applications, along with common EMP protection approaches and current testing methods used to evaluate the resilience of equipment and systems exposed to an EMP attack.

Designing safe products powered by lithium-ion batteries requires an understanding of how the battery pack will behave while undergoing thermal runaway. In this work, fractional thermal runaway calorimetry is used to estimate the energy release from cells at different states of charge when undergoing a thermal runaway.

Keysight Technologies, Inc. introduces RFPro Circuit, a next-generation radio frequency (RF) simulation tool targeting the complex, multi-physics requirements of today's RF integrated circuit (RFIC) designers.

In today’s ever-changing world, nothing ever stays the same! That trend reportedly extends even to the tenets of Fourier’s Law, a 200-year-old science-based principle that defines how heat diffuses through solid materials.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.

The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.

ESD “event detectors” have been used for years in factory environments to identify and remediate ESD discharges during manufacturing. Now design engineers are embedding system-level and on-chip ESD detection technologies into their systems to analyze and recover from both factory and field ESD events.

This article offers some useful insights and guidelines on how to effectively design and test systems using wide band gap devices to optimize product performance and achieve EMC compliance.