The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer. Implications of EMC-ESD immunity co-design will be reviewed along with several case studies.
The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.
ESD “event detectors” have been used for years in factory environments to identify and remediate ESD discharges during manufacturing. Now design engineers are embedding system-level and on-chip ESD detection technologies into their systems to analyze and recover from both factory and field ESD events.
This article offers some useful insights and guidelines on how to effectively design and test systems using wide band gap devices to optimize product performance and achieve EMC compliance.
This article describes a practical way to improve signal integrity of typical interfaces on the PCB when using external ESD devices.
Most EMI issues are caused by a resonance that is excited somewhere in the system. It may be a resonance of a cable acting as an antenna or a heatsink energized by the power electronics switches bolted to it, becoming a good radiator. In this article, we look at the indicators that signal the presence of structural resonances and provide techniques for fixing the EMI issues. Practical case studies are presented to demonstrate the techniques.
Reliability issues need to be continuously addressed during technology development as technologies further advance into novel transistor structures such as FinFETs and Multi-gate devices.
The growing application of lithium-ion batteries brings with it an increased risk of unanticipated energy releases and thermal runaway. Quantifying battery energy release characteristics during product design can help mitigate those risks.
Implementing a process of EMC compliance for a specific project is much more than simply ensuring that the design engineers follow a long list of “do’s and don’ts” in the form of EMC design rules. Following this process will reap benefits when EMC performance is evaluated at the end of the design process.
This month’s column is the last of three parts devoted to designing, testing, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.