Get our free email newsletter

design

Why ESD Electronic Design Automation Checks are So Critical: Part 1

This article introduces an upcoming Technical Report (TR18) from the ESD Association on Electronic Design Automation checks. It details integrated ESD verification throughout IC design phases, covering schematic-based topological checks and layout-based verification to ensure comprehensive ESD protection in modern circuits.

Design and Operation of Antennas

Looking beyond the equipment, EMC compliance hinges on precise antenna performance. This blog examines how construction materials, proper setup techniques, and regular maintenance affect measurement accuracy. Learn why high-conductivity metals, careful calibration, and consistent care are essential for reliable testing that ensures your products meet regulatory standards.

Designing for EMC Compliance in Consumer Electronics

This practical guide explores the critical challenges of electromagnetic compatibility in modern consumer electronics, from smartphones to wearables. Learn key design strategies for managing interference in increasingly compact devices with real-world examples. 

Filter Designs for Switched Power Converters: Part 2

This series of articles delves into the design principles of power filters for switched-mode power converters and similar applications, focusing on conducted and radiated emissions. Part 2 will examine specific aspects of switched power converters.

IEEE Announces Student EMC Hardware Design Competition

IEEE's EMC Society invites students to compete in an RF source location challenge at the EMC+SIPI Symposium in Raleigh, NC. Three finalists will hunt hidden transmitters, with cash prizes awarded to the top performers.
- From Our Sponsors -

Tackling Low-Voltage Signaling in Inverter Design: Part 2

Discover practical strategies for managing noise in high-power inverter designs. From component selection and PCB stack-up to routing techniques, learn how to protect sensitive low-voltage signals while maintaining system performance. Essential reading for engineers working with mixed-signal power electronics designs.

Tackling Low-Voltage Signaling in Inverter Design: Part 1

Often, low voltage signaling issues are silent during the initial evaluation phase of product development, and once the power is turned up suddenly, communication stops being reliable. By identifying key analysis steps at each stage of the design process, this two-part article will help you plan, identify, and solve these issues.

EMI Shielding and Thermal Interface Considerations for Commercial and Defense Drone Technology

Electromagnetic interference (EMI) and excessive heat pose considerable risk to the proper operation of electronic systems within commercial and defense drone technology. By implementing solutions such as EMI shielding products and thermal interface materials, engineers and product designers can mitigate risks and meet regulatory requirements needed for high reliability and performance.

Filter Designs for Switched Power Converters − Part 1: Overview

This series of articles delves into the design principles of power filters for switched-mode power converters and similar applications, focusing on conducted and radiated emissions. Part 1 provides an overview of filter design principles, emphasizing the need for specialized approaches to meet EMC specifications in an increasingly electrified and sustainable world.

Advanced CDM Simulation Methodology for High-Speed Interface Design

A Charged Device Model (CDM) simulation method has been demonstrated to predict CDM fail current of receiving circuits with gate oxide connected to pad. This method involves inclusion of 20ps rise time edge into the stimulus. It was shown previously that this fast rise time component of the pulse can cause the gate oxide damage. The simulation method is intended as a schematic-level tool during pre-silicon design phase to deliver CDM ESD protection. Simulation results are verified by silicon results with qualification CDM test on package and Transmission-Line-Pulse (TLP) measurements on wafer-level.
- From Our Sponsors -

Digital Sponsors

Become a Sponsor

Discover new products, review technical whitepapers, read the latest compliance news, and check out trending engineering news.

Get our email updates

What's New

- From Our Sponsors -

Sign up for the In Compliance Email Newsletter

Discover new products, review technical whitepapers, read the latest compliance news, and trending engineering news.

Close the CTA