Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.
Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has been steadily shrinking over time due to technology scaling not only from a smaller feature size but ... Read More...
CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.
The voltage based CDM classification has practically no meaning for IP qualification. In this article, we propose an alternative CDM qualification, which is based on a peak current criterion.
The charged device model describes the electrostatic discharge (ESD) event that occurs when an integrated circuit (IC) is rapidly charged or discharged through a single pin to a metallic surface.
There are several scenarios where integrated circuits (ICs) are mounted on printed circuit boards (PCBs) which might be charged-up and experience CDM-like events.
Many sources recently have reported that electrical failures to components previously classified as EOS (Electrical Overstress) are instead the result of ESD (Electrostatic Discharge) failures due to charged-board events (CBE) [1,2]. A charged printed circuit board assembly stores substantially more charge than a discrete device as its capacitance is larger. A subsequent discharge of the board assembly results in increased current for that event - versus that of the discrete component. Consequently, a device’s CDM (charged device model) rating is lowered when mounted in a printed circuit board (PCB). In an attempt to get a feel for just how much it is lowered, we conducted CDM stress tests on components in discrete form, and again after insertion into larger and larger sized pc boards. We found that the CDM ratings are lowered dramatically!
In earlier articles in this publication we have discussed the charged device model (CDM) testing of small devices. In the first article we demonstrated that the peak current for small devices does not become vanishingly small.1 The commonly held belief of vanishing current for small devices was shown to be an artifact of measuring the current with the 1 GHz oscilloscope2 specified in the JEDEC CDM standard.6 The second article explained various ways to make CDM testing of small devices more reliable with the use of small surrogate packages, or the use of templates to hold the device during testing.3 In this article we will show how insight can be gained into the CDM testing of small devices using a simple three capacitor circuit model.4, 5
Integrated circuits are tested for their robustness to electrostatic discharge (ESD) using the Human Body Model (HBM) and Charged Device Model (CDM) test methods. Circuits which pass 1000 V HBM or 250 to 500 V CDM can be handled with high yield in manufacturing facilities using basic ESD control procedures. [1, 2] HBM is the oldest, best known and most widely used ESD test method, but most ESD factory control experts contend that the vast majority of ESD failures in modern manufacturing lines are better represented by the CDM test method. The CDM test method is intended to reproduce what happens when an integrated circuit becomes charged during handling, and then discharges to a grounded surface.