cdm

Real-world ESD discharge currents during semiconductor assembly differ dramatically from standard test predictions. A new Discharge Current Sensor reveals that actual currents are lower but faster than expected, challenging current protection designs for Multi-Chip Modules and Systems in Package.

Traditional Charged Device Model testing falls short for bare dies in 2.5D/3D devices. With discharge currents reaching 500 mA at just 5V, existing methods can't handle the unique challenges of testing unpackaged components. CCTLP emerges as a promising alternative for reliable low-voltage testing.

The charged device model spark itself is not just resistive; it often has extra inductance or L-C energy storage. These plus hardware properties affect the CDM waveform and affect methods to correlate alternate CDM test methods to standard JEDEC CDM.

A Charged Device Model (CDM) simulation method has been demonstrated to predict CDM fail current of receiving circuits with gate oxide connected to pad. This method involves inclusion of 20ps rise time edge into the stimulus. It was shown previously that this fast rise time component of the pulse can cause the gate oxide damage. The simulation method is intended as a schematic-level tool during pre-silicon design phase to deliver CDM ESD protection. Simulation results are verified by silicon results with qualification CDM test on package and Transmission-Line-Pulse (TLP) measurements on wafer-level.

It is now well known that testing for CDM ESD evaluation is becoming a bigger challenge. An alternate approach called capacitively coupled transmission line pulsing (CCTLP) offers advantages over standard field-induced CDM testing.

This blog explains CDM ESD testing using the field-induced (FI) method, which is important for semiconductor manufacturers. It covers building a CDM-FI tester, waveform details and verification, and qualification nuances. 

As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.

Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.

The 16.6 ohm implementation of contact CDM (LICCDM) recently published in ANSI-ESD Standard Practice 5.3.3 is shown to produce waveforms of similar shape, I_fail, and I_peak vs. C_eff dependency as JS-002. The non-monotonicity of JS-002 at low voltages is overcome using LICCDM. A path to joint standardization with air discharge testing is proposed.