cdm

This blog explains CDM ESD testing using the field-induced (FI) method, which is important for semiconductor manufacturers. It covers building a CDM-FI tester, waveform details and verification, and qualification nuances. 

As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.

Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.

Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.

The 16.6 ohm implementation of contact CDM (LICCDM) recently published in ANSI-ESD Standard Practice 5.3.3 is shown to produce waveforms of similar shape, I_fail, and I_peak vs. C_eff dependency as JS-002. The non-monotonicity of JS-002 at low voltages is overcome using LICCDM. A path to joint standardization with air discharge testing is proposed.

Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has...

Historical Background  CDM is an important model for ESD qualification. The well-known CDM refers to...

CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.

The voltage based CDM classification has practically no meaning for IP qualification. In this article, we propose an alternative CDM qualification, which is based on a peak current criterion.

Updates to Past CDM Open Forum Questions