Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.
The 16.6 ohm implementation of contact CDM (LICCDM) recently published in ANSI-ESD Standard Practice 5.3.3 is shown to produce waveforms of similar shape, Ifail, and Ipeak vs. Ceff dependency as JS-002. The non-monotonicity of JS-002 at low voltages is overcome using LICCDM. A path to joint standardization with air discharge testing is proposed.
Can you continue aiming for typical CDM protection levels? Introduction The ESD Design Window (ESD-DW) has been steadily shrinking over time due to technology scaling not only from a smaller feature size but ... Read More...
Historical Background CDM is an important model for ESD qualification. The well-known CDM refers to the discharge of an IC package to a grounded surface, whether from automatic handlers in a production area o... Read More...
CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.
The voltage based CDM classification has practically no meaning for IP qualification. In this article, we propose an alternative CDM qualification, which is based on a peak current criterion.
Updates to Past CDM Open Forum Questions
The charged device model describes the electrostatic discharge (ESD) event that occurs when an integrated circuit (IC) is rapidly charged or discharged through a single pin to a metallic surface.
There are several scenarios where integrated circuits (ICs) are mounted on printed circuit boards (PCBs) which might be charged-up and experience CDM-like events.
In earlier articles in this publication we have discussed the charged device model (CDM) testing of small devices. In the first article we demonstrated that the peak current for small devices does not become vanishingly small.1 The commonly held belief of vanishing current for small devices was shown to be an artifact of measuring the current with the 1 GHz oscilloscope2 specified in the JEDEC CDM standard.6 The second article explained various ways to make CDM testing of small devices more reliable with the use of small surrogate packages, or the use of templates to hold the device during testing.3 In this article we will show how insight can be gained into the CDM testing of small devices using a simple three capacitor circuit model.4, 5