Updated Trends in Charge Device Model (CDM)
As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder.
Low Voltage Charged Device Model (CDM) Testing at a Crossroads
Most ESD experts consider CDM testing to be the most critical ESD qualification test for modern integrated circuits. ESD control engineers need to know the charged device ESD robustness of all components passing through their manufacturing line. CDM measurements provide that knowledge.
What Are the Advantages of Capacitively Coupled TLP (CC-TLP)?
Within the past 18 years, many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC-TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature.
Toward Standardization of Low Impedance Contact CDM
The 16.6 ohm implementation of contact CDM (LICCDM) recently published in ANSI-ESD Standard Practice 5.3.3 is shown to produce waveforms of similar shape, Ifail, and Ipeak vs. Ceff dependency as JS-002. The non-monotonicity of JS-002 at low voltages is overcome using LICCDM. A path to joint standardization with air discharge testing is proposed.
Advances in CMOS Technologies Leading to Lower CDM Target Levels
Can you continue aiming for typical CDM protection levels?
Introduction
The ESD Design Window (ESD-DW) has been steadily shrinking over time due to technology scaling not only from a smaller feature size but ... Read More...
Evolution of Charged Device Model ESD Target Requirements
Historical Background
CDM is an important model for ESD qualification. The well-known CDM refers to the discharge of an IC package to a grounded surface, whether from automatic handlers in a production area o... Read More...
Device Failure from the Initial Current Step of a CDM Discharge
CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.
Qualification of Interface IP for Charge Device Model Based on Peak Current
The voltage based CDM classification has practically no meaning for IP qualification. In this article, we propose an alternative CDM qualification, which is based on a peak current criterion.
ESD Open Forum
Updates to Past CDM Open Forum Questions
Next Generation Charged Device Model ESD Testing
The charged device model describes the electrostatic discharge (ESD) event that occurs when an integrated circuit (IC) is rapidly charged or discharged through a single pin to a metallic surface.