The verification of electrostatic discharge (ESD) protection in a complex integrated circuit (IC) design is extremely challenging. Leading-edge designs have many supply domains and voltage levels for different functional parts like radio frequency (RF), digital and high voltage blocks, making ESD checking a complex and error prone task. Relying on manual verification alone poses a significant risk of missing design flaws, which can be very costly during manufacturing and in the field. Consequently, automated ESD checking is highly desired in today’s design flow. This article outlines the essential requirements of the ESD verification flow as defined by the ESD Association (ESDA) Electronic Design Automation (EDA) Tool Working Group [1].
