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Decoupling Capacitor Design on PCBs to Minimize Inductance and Maximize EMI Performance

Introduction There are many different opinions about the best decoupling capacitor strategy for printed circuit...

I’m Partial to Partial Inductance!

1409 F2 coverIt is well known (but often forgotten) that the concept of inductance, without defining a complete loop of current, is completely meaningless! Some books give inductance of a length or wire, some people talk about the inductance of a via, and still others talk about the inductance of ground braids, etc. All these discussions about inductance ignore the requirement for a complete loop before the total or loop inductance can be discussed in any meaningful way.

Using EMC Tools to Help Designs Pass the First Time

1408 F1 coverThis is a true story. When I first joined IBM as an EMC engineer, my new manager handed me a document titled ‘EMC Design Process at IBM’ and asked me to comment. I quickly read the short document that basically said that the EMC engineer would provide the design engineers a list of EMC rules, which would be largely ignored.

Differential Mode to Common Mode Conversion on Differential Signal Vias Due to Asymmetric GND Via Configurations

1406 F3 coverThis article investigates the impact of ground vias placed in close proximity to high speed differential signal vias and the resulting differential mode to common mode conversion. The work shows the influence of the distance between ground (GND) vias and differential signal (Diff. SIG.); the effect of the asymmetrical configuration of the GND vias; the impact of the dielectric thickness and the number of transitions between the planes.

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