Automotive High-Speed Interfaces: Future Challenges for System-Level HV ESD Protection and First-Time-Right Design
This paper describes future design challenges of discrete system-level ESD protection (high-voltage, low-capacitance) of automotive high-speed data links such as multi-gigabit ETHERNET and SERDES/video-links. A special focus is put on an in-depth analysis and accurate modeling of the complex ESD behavior of the Common Mode Choke (CMC).
