Managing High-Power Inverter Noise to Protect Low-Voltage Signals

In Part 1 of this two-part article (see In Compliance Magazine, December 2024), we discussed the challenges involved in designing, building, and debugging a high-power mixed-signal inverter, and examining common application-specific integrated circuits (ASICs) that work alongside FETs (field effect transistor) and MCUs, focusing on their roles in interfacing and driving. In Part 2, we’ll discuss the importance of choosing the correct PCB stack up during component selection and placement, as well as component and layout mitigation strategies.

Components for Mitigating Coupled Noise

Mitigating the impact of transient signals on inverter systems requires a combination of component-level solutions and effective PCB design practices. Equally important are layout and routing techniques. In the following sections, we’ll dive into discussing several component selection strategies a designer can choose early on to protect against these types of failures, and then cover routing and stack-up techniques to minimize noise and interference.

The Schmidt Trigger or Buffer

The primary challenge in interfacing with gate driver ASICs and other components that use a reduced VIO is managing the signal-to-noise ratio, which includes the intended signal, and the noise generated by electrical transients coupled onto the victim trace or the shared reference plane. One effective solution is the use of an external buffer or Schmitt trigger (see Figure 1). These devices, referenced at a higher VIO referenced to VDD, thus offer greater robustness against transients and ground bounce, much like the MCU’s output drive circuitry.

Key electrical characteristics to consider include:

• Operating temperature of the buffer since, the warmer the inverter gets due to its proximity to the output stage of the device, the greater the likelihood that the operating point will shift;
• Ensuring that the propagation delay from input to output does not impact the functionality of the drive signal or the communication bus;
• Verifying that the VIH and VIL thresholds are compatible with your gate driver IO voltage and sufficiently high to provide immunity from stray transients; and
• Paying attention to the type of signal being buffered or level shifted. A driven IO signal, such as SPI or a low-side gate drive input, does not require a pullup resistor like I2C.

Additionally, it is crucial to ensure that the buffer is powered and ready at the time of communication and actuation. Also, care must be taken to analyze the power rail and reset values should there be a momentary dropout or power cut of the buffer. Overall, this device is particularly effective, though expensive, in single board designs where space constraints prevent adequate physical separation between victim and aggressor traces.

As for placement, it depends upon the type of crosstalk you’re getting since you’re looking to utilize the higher VIH/VIL thresholds of the buffer. You generally want to place the component close to the gate driver since any transient signals coupled onto the trace will have a harder time coupling (see Figure 2). Placing it near the MCU can leave the trace as an antenna, which is less effective.

Terminating Components

If your design cannot accommodate the overhead buffer circuitry for noise immunity, the next best strategy is to leverage the inherent capacitance of the trace running from the MCU to the gate driver ASIC. By adding a series termination resistor, you create a small low-pass filter that helps snub transient signals. A common recommendation in early prototype designs is to include the pads for these components and connect them with either a solder bridge or a 0-ohm resistor (see Figure 3).

Again, you’ll want to use your best judgment in terms of near end (near the MCU) or far end (near the gate drive ASIC, see Figure 4). You’ll have more parasitic capacitance the more of the trace you leave and further away it’s placed to the ASIC, depending on which component end is driving the pulses.

Additionally, adding a small parallel capacitor to ground can enhance the filtering effectiveness, depending on the drive strength of the signal. The key is to add enough capacitance to effectively filter transient glitches without impacting critical factors such as the rise and fall times of the propagating signal. Incorrect communication timing or control could result if these factors are compromised. In communication signaling, setup and hold times, as specified in the ASIC datasheet, are particularly sensitive to these changes.

While managing noise on the victim’s side is effective, addressing the high voltage side is equally important. Designers can use two main techniques to protect against transients: snubber circuits and slowing down the edge rate (either through drive strength modifications of the gate drive strength; or a physical resistance in the gate path).

RC Snubber Circuits

Implementing an RC snubber circuit on the high voltage side can mitigate high-frequency ringing during the switching rise and fall time which improves EMI. This can be done using a resistor-capacitor snubber to ground across V_gs or decoupling capacitors across V_ds. An example is shown in Figure 5.

The snubber circuit is designed to dampen oscillations and absorb the excess energy from switching transients. Typically, the values of the resistor and capacitor are chosen based on the ringing frequency and the impedance of the circuit. A typical procedure might suggest starting with a capacitor value that resonates with the parasitic inductance at the ringing frequency, and then tuning the resistor to critically dampen the oscillation. Note that, while adding snubber circuity (or placeholders for snubbers) is useful, their usage will create power loss.

It’s typical for a designer to place the snubber structures as close as possible to the switching device to minimize parasitic inductances and capacitances that could negate the snubber’s effectiveness, thus increasing the heat dissipated across R_S .

Slowing Down the Rise Time

Slowing the output drive speed by adding a series resistor from the output of the gate driver to the input of the power FET, or modifying the drive strength of the smart ASIC, can also help manage noise. The value of the gate resistor is the ability to select the rise and fall times of the FET gate voltage, thereby reducing the di/dt and dv/dt during switching.

Application notes typically recommend starting with a small resistor (e.g., 10-20 ohms) and adjusting based on performance, both EMI (electromagnetic interference) and efficiency. In addition, the designer can choose the drive strength, usually represented as either percentages (the appropriately named fast/nominal/slow) or in amps.

Snubber circuits and controlling the edge rate are straightforward solutions to incorporate during the design phase by including appropriate pads near the gate drivers and populating them as needed. However, these options have efficiency trade-offs:

• Increased deadtime—Slowing down the gate drive signal increases the need for deadtime, resulting in more off-time and reduced efficiency; and
• Power dissipation—Snubbing the drive signal to reduce ringing dissipates energy as heat in the resistor-capacitor combination. The power dissipation in the snubber resistor can be significant and must be considered in thermal management planning.

Whether using a more robust solution like a buffer or adding critical components to key areas, component choice and placement can provide essential last-minute solutions.

Next, we’ll explore stack up, routing and grounding.

Stack Up

When sitting down to layout the schematic, it’s important to keep in mind a list of objectives that the design must accomplish in order to help naturally keep sensitive nets sufficiently isolated. These objectives are similar to that of a high-speed layout, with the following major differences:

• A complete assembly usually focuses on including as much reference plane as possible to ensure proper heat and to meet rigidity concerns;
• The power levels that the assembly supports on both the input DC bus and the output generally requires “fingers” around each phase connection on exposed layer power planes to support the higher currents necessary; and
• Depending on circuitry needed for communication and logging, the fanouts and low voltage traces are limited to drive traces, CAN or ethernet communication, and sensors.

These last two points specifically can allow the design to focus mostly on impedance continuity, as there should be fewer traces to cut up internal reference planes, and power is generally fed via power planning due to the current amplitudes involved.

With that said, the options to consider in a design include the number of layers and planes, the ordering of those layers, and the spacing between the layers. Considering these design constraints, we can define the following traditional objectives when deciding on a stack up to help shield your sensitive traces from high voltage ones and to help with component placement:

1. A signal layer should always be adjacent to the plane;
2. Signals should be routed adjacent to the plane in which the components are referenced, which often results in the use of two reference planes;
3. When a power plane is used, it should be placed close together to a reference plane;
4. When possible, use reference layers to sandwich traces you want to either shield or keep from radiating; and
5. Using more than one reference plane is very advantageous in design as it provides shielding and low impedance.

In most designs, you will generally see options #2 and #3 difficult to achieve simultaneously. As such, it’s recommended to err on the side of multiple dedicated reference planes that are tied together at multiple points vs. a mixed reference and power plane. Nevertheless, combining these objectives and characteristics in a unique inverter design, we can come up with the example stack ups shown in Figure 6.

The recommendations for a four-, six- and eight-layer board shown in Figure 6 help provide a foundation for the designer to start with. In addition to layer designation, the design also can further control coupling by changing the spacing between the various layers.

If the goal is to create tighter signal coupling between adjacent layers of the same signal type, the design then makes the interlayer spacing between these two groups thicker to allow for more isolation. An example of this is shown in Figure 7.

Additionally, if cost allows, a carrier board concept allows for natural isolation between the low voltage and high voltage side of the system, interfaced at a specific header connection (see Figure 8). The added benefit here is that the isolation of low voltage referencing and signal planes are more naturally confined to the carrier board, and it allows you to swap to different power boards. The downside is that the form factor of the design is now a concern and added cost.

Regardless of form factor or stack up you use, we now need to address the next challenge, which is how to best take advantage of these options when planning a design.

The answer to this question is to first identify the component categories, and thus their associated traces, and separate them into high and low voltage. By doing this, we keep a twofold goal in mind, first to keep high-power circulating return currents away from low voltage victim traces and, second to ensure a low impedance return path for those currents, preventing noise voltages from coupling onto victim traces.

This proposed methodology splits signals into small and large signal referencing and routing planes. An example using an earlier diagram is shown in Figure 9, where we room or separate the components into high (red) and low voltage signaling (blue). 

The signals and their references are described as:

• Low voltage PWM GPIO and communication lines (I2C/SPI), which should be referenced to a plane separate from the “high power” plane, with their traces adjacent to it. Often, you’ll see terms like signal ground (s), digital ground (d), or analog ground (a) used to describe these low-voltage references. In general, they should encompass the space between the MCU and associated ASIC components (gate drives).
• Large signal referencing, which generally refers to high side PWM GPIO and their drive signals, should be referenced to a “high power” plane, where schematic symbols and pins refer this to power ground (p).

The goal is to apply the aforementioned rules, reference similar signal types together to the same plane, and then bond those planes together which reduces loop area and coupling. Additionally, to handle the current density denoted by the higher power ratings, the inverter phases and DC bus tend to form fingers that encompass the path between the DC link, bus capacitors to the power FETs, and phase connections. This can make decoupling any high-frequency transients associated with these FETs challenging due to space constraints. Therefore, the layers should be chosen in such a way as to be able to decouple in the smallest loop area possible.

Finally, when planning for the interconnection of these various plane layers together, it’s tempting to try and galvanically isolate the high voltage switching (“noisy ground”) and low voltage (“quiet ground”) with strict adherence but often without care as to how these concepts play into the modules “system ground.” 

• By galvanically isolating, or otherwise offering a single point of connection, which creates the possibility of high impedance interconnections, resulting in an increase in common mode noise voltages and currents; or
• Physical cuts in the plane, either via trace or removal of copper for galvanic isolation, which can result in an increase in radiated emissions as currents capacitively couple across the discontinuities. 

Both scenarios should be avoided to maintain signal integrity and reduce noise.

An example of a single-point connection between reference planes is shown in Figure 10, in which any electrical transients referenced to AGND but coupled onto a trace referenced to GND will have to travel back through this single-point connection.

Another example is shown in Figure 11, this time I²C lines from an ASIC going to a level shifter.

The light blue is the I²C’s reference plane, meaning any electrical transients coupled onto that plane must traverse through that small plane through a single point connection to the system, reference on the top left of the light blue polygon.

In the last section of this article, we’ll introduce the concept of rooming as a precursor to actual design.

Connector and Component Placement

The design constraints imposed upon an inverter module aren’t limited to mitigation of electromagnetics, but also to address cooling and ruggedness considerations. And, for that reason, designers will often find themselves working with a PCB assembly whose form factor and cooling requirements are already given to them, rather than designing a case around the assembly. And, as such, a popular strategy that should always be applied before designing any circuit board is floor planning using your favorite diagramming tool. This allows visualization of three key areas of an inverter and their relation to phase cabling:

• Low voltage signaling—Typically made up of an MCU and supporting devices (such as flash, Ethernet or CAN PHY, and sensors), and half of the gate driver circuit.
• High voltage input section—Includes input connectors that carry the brunt of the power from the bus voltage and the DC bus caps that stabilize the DC bus during actuation.
• High voltage switching section—Comprises various sections of the three phases, the output switches, and the other half of the gate driver.

An example of a floor plan and how it can help visualize planning currents is shown in Figure 12. In the example to the left, there is a risk of signals running near each other causing unintended coupling. In the example to the right, placing the connector farther away reduces the concern. 

Conclusion

With the push across various industries to hybridize machines that would otherwise be pneumatic or hydraulically driven, inverters are becoming prolific. This two-part article details the importance of starting with a solid foundation, first by creating a rooming plan, and then choosing the correct PCB stack up during component selection and placement, including placeholders for components that otherwise can be unpopulated. These decisions, when done early, allow the designer flexibility when an otherwise difficult-to-diagnose problem comes up, such as incorrect actuation of a gate drive, or communication lines causing the software to lock up.