Contact First Methods

This column is the third in a three-part series on testing small form factor products for CDM. Part 1 highlighted the issues of CDM testing with the current field-induced CDM (FICDM) testers. The main problems are first the pogo pin size vs package or ball bump size and second small form factor products may have very low withstand voltages where the FICDM testers are known to be unreliable. Part 2 highlighted solutions that were still air discharge. In Part 3, solutions where contact to the part is made first and then a stress similar to a CDM stress is applied. These solutions are not air discharge.

Contact First Options for Bare Die and Interface Die Testing

Capacitively Coupled Transmission Line Pulsing – CC-TLP

The capacitively coupled transmission line pulsing (CC-TLP) [1][2] allows a reproducible CDM-like stress test. It uses a VF-TLP pulse generator with a rectangular stress pulse. Unlike VF-TLP, in which both pins are connected to the DUT, CC‑TLP connects only the signal pin directly to the DUT, while the ground return path is a capacitive connection.

Figure 1 depicts a possible setup for CC-TLP. The DUT is placed on the chuck of a wafer prober. The VF-TLP system generates the pulse, which passes the pick-off for the pulse voltage measurement and is then injected into a 50-ohm transmission line. The transmission line’s ground shield connects to the ground plane, and the signal line is connected to a probe needle, which connects to the DUT through a small hole in the ground plane. The voltage and current flowing at the DUT pin as a function of time can be calculated from the sum and difference of the incident and reflected pulses.

Tests can be performed both at wafer/die‑level but also at package-level. This allows CDM‑relevant investigations without the need for packaging. Furthermore, the high reproducibility improves the determination of the failure threshold by applying smaller stress steps. This becomes relevant regarding the trend of reducing the required CDM thresholds for modern deep submicron technologies.

The repeatability range for the CDM data in the 110‑volt charge voltage region shows a variation in a range of 30%, with some outliers in a range of 40%. In contrast, the variation of the CC-TLP peak currents is in the range of 5%. Note that there is no correlation between the precharge voltages of the two methods for the same peak current.

Many studies exploring 3 µm to 7 nm technologies have demonstrated the excellent correlation of CC‑TLP with CDM in terms of stress current failure threshold as well as electrical failure and physical damage signature [3][4][5].

Low Impedance Contact Charge Device Model – LI‑CCDM

Low impedance contact CDM (LI-CCDM) outlined in ESD SP5.3.3 [6] was originally developed for testing of packaged devices. However, the technique can be adapted to wafer-level and bare die testing. LI-CCDM provides an air discharge-free CDM test method that is capable of lower stress levels.

The connection to the pogo pin is very different in LI‑CCDM than in field-induced CDM. Figure 2 shows a diagram of an LI-CCDM system. The coupling plane is the field plate from ANSI/ESDA/JEDEC JS-002, but it is tied to ground with the isolation resistor rather than charged to a high voltage. The ground plane size is also the same as in ANSI/ESDA/JEDEC JS-002, and it has a similar pogo pin for contacting the device being tested.

In LI-CCDM, the pogo pin is connected to two 50-ohm coaxial cables and a 50-ohm resistor to the ground plane. Assuming the coaxial cables are terminated with 50 ohms at the far end, the parallel combination of the two 50-ohm cables and a 50-ohm resistor creates a 16.7-ohm source impedance. Thus, 16.7 ohms is very close to the resistance of a typical FICDM spark. One of the coaxial cables is used to supply the stress to the device being tested, while the other is connected to an oscilloscope, which measures the stress voltage. The stress is supplied by a discharge from a short coaxial cable charged to the desired voltage. Due to the impedance, approximately three times the amount of voltage is required to deliver the same amount of current for a given ANSI/ESDA/JEDEC JS-002 waveform. Discharge of the coaxial cable produces a rectangular pulse whose duration is controlled by the length of the coaxial cable. The capacitor and 50-ohm resistor at the left end of the cable in Figure 2 prevent reflections. [7][8]

Relay Pogo Contac Charged Device Model – LI‑CCDM

Relay probe contact CDM (RP-CCDM) is a mercury relay-based, contact-first discharge method for generating CDM stresses [9]. The RP-CCDM allows for a repeatable relay discharge in the probe pin while largely preserving the design parameters of ANSI/ESDA/JEDEC JS-002. A simplified schematic of the discharge head is shown in Figure 3.

The following test sequence prevents discharges before the intended CDM stress:

• The field plate is at ground potential with the assumed neutrally charged die on the field plate.
• The relay is closed to ensure the probe tip is at zero potential before contact with the DUT.
• The probe tip is brought into contact with the pin under test.
• The relay is opened.
• The field plate is slowly raised to a high potential, capacitively coupling the DUT to a high potential.
• The relay is closed, initiating the discharge.

Summary

The standardized FICDM tester with a pogo pin is unsuitable for bare-die or wafer-level (including 2.5D/3D microbump D2D interfaces) CDM testing. This paper introduced three contact-first methods to test small form factor parts. The first used a VF-TLP system and capacitively coupled the ground return to get a capacitively coupled TLP. This system is a 50-ohm system. The second took a similar approach but used two cables in parallel and in parallel with a 50-ohm resistor to get 16.7 ohms, which matches the air discharge CDM impedance and hence is called low impedance CCDM. And the third used a relay so that the part can be contacted first, and a discharge is second. This is the relay pogo CCDM method.

These are all viable options for bare-die CDM testing. There is no consensus on which one of these options is the best. The three-part column is an attempt to introduce the issues with testing small form factor parts at low CDM withstand voltages and offer solutions to these problems.

Acknowledgements

This three-part publication is part of a summary of a technical report published by the ESD Association. We would like to acknowledge the authors of that technical report: Robert Ashton (retired), David Epps (AMD), Jared Floyd (ESDEMC), Wei Huang (ESDEMC), David Klien (pSemi), Tom Meuse (Thermo Fisher), Kathleen Muhonen (Qorvo), Friedrich sur Nieden (Infineon), Paul Phillips (Phasix), Michael Reardon (ESDEMC), Masnori Sawada (Hanwa), Jasmine Shen (ESDEMC), Marko Simicic (IMEC), Heinrich Wolf (Fraunhofer)

References

1. H. Wolf, H. Gieser, W. Stadler, and W. Wilkening, “Capacitively Coupled Transmission Line Pulsing CC‑TLP – A Traceable and Reproducible Stress Method in the CDM-Domain,” Journal of Microelectronics Reliability, Elsevier, volume 45, no. 2, 2005.
2. H. Gieser, H. Wolf, and F. Iberl, “Comparing Arc‑free Capacitive Coupled Transmission Line Pulsing CC-TLP with Standard CDM Testing and CDM Field Failures,” Tagungsband 9, ESD‑Forum Berlin 2005.
3. H. Wolf, H. Gieser, K. Bock, A. Jahanzeb, C. Duvvury, and Y. Lin, “Capacitive Coupled TLP (CC‑TLP) and the Correlation with the CDM,” EOS/ESD Symposium 2009.
4. J. Weber, H. Gieser, H. Wolf, L. Maurer, K. T. Kaschani, N. Famulok, R. Moser, K. Rajagopal, M. Sellmayer, A. Sharma, and H. Tamm, “Correlation study of different CDM testers and CC-TLP,” EOS/ESD Symposium 2017.
5. H. Wolf, H. Gieser, D. Walter, “Investigating the CDM Susceptibility of ICs at Package and Wafer Level by Capacitive Coupled TLP,” EOS/ESD Symposium 2007.
6. ANSI/ESD SP5.3.3 – Charged Device Model (CDM) Testing-Component Level Low-Impedance Contact CDM as an Alternative CDM Characterization Method.
7. Simicic, M., Wu, W.-M., Jack, N., Tamura, S., Shimada, Y., Sawada, M., and Chen, S.-H., “Optimization of wafer-level low-impedance contact CDM testers,” EOS/ESD Symposium Proceedings 2020.
8. M. Simicic et al., “Wafer-Level LICCDM Device Testing,” 2021 43rd Annual EOS/ESD Symposium (EOS/ESD), pp. 1-8, 2021.
9. M. Drallmeier, L. Zeitlhoefler, H. Yang, W. Huang, F. zur Nieden, D. Pommerenke, “A Relay Discharged FICDM Method for Improved Repeatability,” EOS/ESD Symposium 2020.
10. Kathleen Muhonen, “Small Form Factor CDM Testing, Part 1: Problems with FICDM Testing for Small Form Factor and Interface Die,” In Compliance Magazine, January 2026.
11. Kathleen Muhonen, “Small Form Factor CDM Testing, Part 2: Air Discharge Options,” In Compliance Magazine, March 2026.

Read Part 1 ¦ Read Part 2