Many of the EMI/EMC problems in electronic products can be avoided or solved with ground (GND) planes. But, be sure your GND plane is a true GND plane.
One of the most dangerous situations for both emissions and immunity in electronic circuits is the possibility to create slots in ground planes and routing signals on top of those slots.
Return currents are distorted as indicated in Figure 1 where a signal in top layer (red color) is crossing the slot created in the GND plane in bottom layer. Note how the return path in that GND plane (blue color) is distorted because the slot.
For that current, the slot works like impedance so a voltage drop is created in the GND system that can excite cables and wires or affect other sensitive areas close to the area.
Slots can be created unintentionally because isolation in pads or connectors, or intentionally as for example when designers try to separate GND planes for different areas (e.g. analog and digital grounds). This is a really dangerous situation!!!.
This month I will show you a simple experiment to see the effect of that kind of slots in a simple PCB board.
In Figure 2 the top layer of our PCB is shown. The bottom layer is a full ground plane with a slot exactly in the area marked with dashed line. Note the ground plane is not seen in this top view of the board.
The BNC connector K5.1 is used to introduce a clock signal (aggressive from EMI point of view) in this circuit.
Jumpers JP.5.1 and JP.5.2 are used to select two paths for the signal: a path crossing a slot in the ground plane (upper part of drawing) and other path with a perfect ground plane for the return (lower part of drawing). Load resistor is R.5.2 with a value of 47ohms and TP.5.1 to TP.5.3 are test points.
The board was scanned with an EMxpert scanner to compare the activity with and without the slot below the clock signal trace.
In Figure 3 emissions from the board in a spectral scan from 10MHz to 200MHz have a difference of more than 25dB. Note the harmonics of the clock and some FM broadcasting ambient noise in the 88-108MHz region.
Additionally, the return current through the slot creates a high frequency ground voltage that usually excites the attached cables to the board and the product will fail in radiated emissions.
It is really interesting to see that activity in a spectral/spatial scan from 10MHz to 200MHz with a resolution bandwidth of 100kHz as in Figure 4.
For the case where clock signal is on top of the slot, clearly current density increases (red color) around the slot. That activity is your real enemy for EMI!
My final advice: NEVER route a critical signal on top of slots in the GND plane and, be careful when designing a PCB with separated grounds. I have solved MANY EMI problems joining grounds, not separating grounds. You can use separate ground if you know really well what you are doing.
Arturo Mediano received his M.Sc. (1990) and his Ph. D. (1997) in Electrical Engineering from University of Zaragoza (Spain), where he has held a teaching professorship in EMI/EMC/RF/SI from 1992. From 1990, he has been involved in R&D projects in EMI/EMC/SI/RF fields for communications, industry and scientific/medical applications with a solid experience in training, consultancy and troubleshooting for companies in Spain, USA, Switzerland, France, UK, Italy, Belgium, Germany, Canada, The Netherlands, Portugal, and Singapore. He is the founder of The HF-Magic Lab®, a specialized laboratory for design, diagnostic, troubleshooting, and training in the EMI/EMC/SI and RF fields at I3A (University of Zaragoza), and from 2011, he is instructor for Besser Associates (CA, USA) offering public and on site courses in EMI/EMC/SI/RF subjects through the USA, especially in Silicon Valley/San Francisco Bay Area. He is Senior Member of the IEEE, active member from 1999 (Chair 2013-2016) of the MTT-17 (HF/VHF/UHF) Technical Committee of the Microwave Theory and Techniques Society and member of the Electromagnetic Compatibility Society. Arturo can be reached at a.mediano@ieee.org. Web: www.cartoontronics.com.
