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Pre-layout Signal Integrity/Power Integrity Simulation Software Expectations

Introduction

Those who may be looking for a signal integrity (SI)/power integrity (PI) simulation software package should have an idea of what functionality and other characteristics they can expect from such a tool during both pre-layout design and post-layout design. This article briefly describes the most important pre-layout elements to look for when selecting a SI/PI software simulation package. The most important elements of post-layout design simulation software will be addressed in a follow-on article.

Pre-layout vs. Post-Layout

The software simulation package should be able to provide functionality to assess designs prior to layout and also post-layout.

During pre-layout design, the simulation software should provide the capability to simulate “what-if” design variations so the design can be “optimized.” By executing SI and PI simulation prior to board layout, designers are better equipped to define post-layout constraints and circumvent performance setbacks that often occur during the last few minutes of the design process, just prior to sending the design package out for initial prototypes.

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During post-layout design, the simulation software should provide the capability to simulate and find nets with poor SI and power distribution networks (PDNs) with poor PI. Simulating “what if” design discrepancies is beneficial since these activities help determine design changes that improve SI or PI. This topic is reserved for a separate follow-on article, and the remainder of this article focuses on the important elements of pre-layout design simulation software.

Pre-layout Design Simulation

A lot of what you want to do in the pre-layout design simulation phase depends on the design behaviors you are most interested in learning about and modeling prior to laying out a printed circuit board (PCB).

For instance, if you’re interested in designing trace and stackup geometries to meet a target characteristic impedance (Z0), then the simulation software selected for this activity should provide a means to determine the signal trace width, trace-to-trace separation (for differential pairs), and stackup properties that produce the target Z0.

If you’re looking at designing vias to meet impedance (Z) and bypassing conditions, then the software simulation package should have the capability to establish the signal via, pad, and antipad characteristics that yield the correct target Z0. For single-ended signals, the simulation software should be able to establish the location and number of stitching vias needed to provide low Z return current paths.

If you’re interested in designing vias to meet acceptable loss requirements, then the software simulation package should include the capability to establish the location and number of stitching vias needed to provide low Z return current paths for signal vias.

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Sometimes you may want to design net topologies to meet crosstalk requirements. If this is the case, then the software simulation package should have the capability to help you optimize design trade-offs and see the effects of manufacturing tolerances that affect crosstalk. You should be able to run repeated SI simulation sweeps to generate design control limits for the post-layout design.

Perhaps you want to establish net properties and terminations that meet signal quality constraints. If this is the case, then the software simulation package should allow you to optimize design trade-offs and see the effects of manufacturing tolerances that affect signal quality. You should be able to run repeated SI simulation sweeps to generate design control limits for the post-layout design.

If your goal is to establish the net properties that meet timing constraints, then the software simulation package should allow you to optimize design trade-offs and see the effects of manufacturing tolerances that affect signal timing. You should be able to run repeated SI simulation sweeps to generate design control limits for the post-layout design.

Maybe you want to establish the power-supply net geometries and stitching via quantities and locations to design power distribution networks (PDNs) with acceptable DC power loss and current density. If this is the case, then the software simulation package should allow you to do just that – design PDNs to meet DC Power loss and current density requirements.

Finally, perhaps you’re interested in designing PDNs to meet low Z requirements across a band of frequencies. In this situation, the software package should allow you to establish power-supply net geometries and decoupling capacitor quantities and locations to design PDNs with acceptable Z across a band of frequencies. Part of the design trade-off study should include the ability to evaluate decoupling capacitor mounting technologies, such as via-in-pad, microvias, and X2Y capacitors, along with the ability to evaluate dielectric properties for embedded capacitors, such as a C-ply material or ultra-thin thickness.

Post-layout Design Simulation

This phase occurs after the pre-layout design activity phase prior to sending the design out for the initial prototype PCB. It should be performed even if the pre-layout design activity phase was skipped. As previously mentioned, the topic of expectations of pre-layout design simulation software will be addressed in a separate follow-on article.

References and Further Reading

  1. HyperLynx® SI/PI User Guide, Software Version 9.4.1

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