Q: The SEED (system efficient ESD design) approach to ESD design promises to provide a systematic procedure for designing ESD protection for electronic systems. Will SEED truly get us away from the trial and error drudgery of system level ESD design?
A: The answer is the frustrating, Yes and No. The SEED approach helps a great deal for protection from ESD stress directly to Input/Output lines such as USB or HDMI. That is, however, only part of the full scope of system level ESD. It will be instructive to review the SEED approach and then discuss the other aspects of System Level ESD which will not be significantly improved by SEED.
The SEED approach is most applicable to an ESD threat directly to a system input or output, as shown in Figure 1. This example is for a stress to one side of a high-speed differential signal. Some high-speed signal standards require an inline capacitor on either the receive or transmit sides to eliminate issues with differences in dc levels between send and receive ends of cables. For a high-speed signal such as USB 3.0 the signal traces must have a controlled impedance or signal integrity will be lost. On a receive line there is a requirement for termination resistors, RT, at the end of signal lines to prevent reflection. These termination resistors may be part of the integrated circuit (IC) driving the differential line or they may be discrete surface mount resistors located directly adjacent to the IC. To provide ESD protection transient voltage suppression, TVS, devices are often included. In Figure 1 the TVS devices are represented as a Zener diode, but for high speed circuits special devices have been developed by a number of manufacturers which have very low capacitance, yet have low impedance when voltages on the signal line exceed their expected values.
ESD design in this case involves several decisions. One of the most important is to choose a TVS device that works well with the IC connected to the input or output line. The TVS must have low enough capacitance to not interfere with signal integrity, but it must also have a low impedance state triggered by an ESD event when voltage exceeds the normal operating range. The TVS’s transition to its low impedance state must happen before damaging currents can enter the IC. Position of the TVS can be important. In some cases, the addition of a small series impedance, RS, between the TVS and the IC can improve ESD robustness with minimal degradation of signal integrity. Trial and error have often been the only approach to find the optimal design.
SEED aims to eliminate the trial and error approach by using circuit simulation tools in the ESD design flow. SEED requires the development of model files which are valid during an ESD event. Models would be needed for the following:
- A source model for the ESD stress
- Model for TVS device including
- Transition from high impedance to low impedance state
- High current IV properties in low impedance state
- Frequency dependence?
- Coupling capacitor during a short current burst
- Models of printed circuit board traces
- Resistors for short high current bursts
- Input circuitry of the IC in the ESD time domain up to the point of damage
Use of these model files would allow simulation of ESD events and allow informed design choices before committing to the first build of a product. The models would likely be based on transmission line pulse (TLP) measurements. The simulations could be carried out in a variety of simulation environments such as SPICE, VHDL-AMS, or VERILOG-A. With this approach ESD design on system input and output lines would become part of a systematic design flow, rather than trial and error. ESDA Working Group 26, System Level ESD Modeling is currently working on procedures for developing both quasi static and dynamic models for System Level ESD Design.
The SEED approach is most straight forward in the prevention of hard failures created by electrically induced physical damage. SEED could also be helpful for soft failures such as data corruption or system upset but will likely require more detailed models and analysis.
ESD stress directly to I/O lines of a system is not the only path for ESD to upset functionality of a system. In fact, direct ESD stress to system I/Os is specifically excluded in the most widely used system level ESD test standard, IEC 61000-4-2 [1], although most system manufacturers do perform some form of ESD stress directly to data lines as part of their internal qualification procedures. The test setup for ESD stress testing required by IEC 61000-4-2 for small systems and table top equipment is represented in Figure 2. The IEC standard specifies a wood table, on a grounded floor with a metal horizontal coupling plane on top of the table, connected to ground with a series pair of 470 kOhm resistors. The equipment being testing is placed on an insulating layer on top of the horizontal coupling plane. The ESD stress is applied to the equipment being tested with an “ESD gun” whose discharge characteristics are specified in IEC 61000-4-2. The discharges are applied to any equipment surfaces which might come in contact by a user’s touch. An emphasis is placed on areas where an ESD event might cause upset or damage, such as keyboards, displays and areas where a discharge could enter the system’s case, such as vent holes and seams. Discharges are also made to the horizontal coupling plane and to a vertical coupling plane placed beside the unit under test. This tests if discharges to nearby objects can cause system upset by electromagnetic coupling. All of these tests are performed on a powered and functioning system. The test results can fall into 4 categories:
- No system upset during testing
- System upset during test, but system returns to normal operation without user intervention
- System upset requiring user intervention to return to normal operation
- Physical damage to the system
The most prevalent failures during system level ESD testing are system upsets, rather than physical damage.
Clearly the SEED approach applied to I/O signal pins will not ensure that a system will be immune to this type of ESD testing. Designing to pass this type of stress requires care in proper system grounding and keeping sensitive circuitry away from possible entry points for ESD in the case. The measurement techniques in ESDA Standard Practice document on Near Field Immunity Scanning [2] can be used to find components and printed circuit board locations which are particularly sensitive to electromagnetic upset.
In summary, the SEED approach, when proper ESD model files are available for all elements in the stress path are available, will create a systematic design strategy to prevent physical damage for ESD stress to system inputs and outputs. The other aspects of system ESD design will need new tools such as 3D field solvers and increased use of scanning tools to locate circuits sensitive to ESD upset.
References
- IEC 61000 “Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test”
- ANSI/ESD SP14.5-2015 “EOS/ESD Association Standard Practice for Electrostatic Discharge Sensitivity Testing – Near Field Immunity Scanning – Component/Module/PCB Level”
Robert Ashton is the Chief Scientist at Minotaur Labs, www.minotaurlabs.com, a provider of ESD and latch-up testing located in Mesa, Arizona. He received his BS and PhD degrees in Physics from the University of Rhode Island. After Post-Doctoral positions at Rutgers University and Ohio State University he joined AT&T Bell Laboratories in the field of integrated circuit technology development. He stayed with Bell Laboratories, and its spinoffs Lucent Technologies and Agere Systems for 23 year where he became involved with on chip ESD protection. After leaving Agere Systems he became Director of Technology of White Mountain Labs, an ESD and latch-up test house. He then spent 10 years with ON Semiconductor in their discrete products division, providing and managing application engineering support for transient voltage suppression products. He has published numerous articles on ESD testing of integrated circuits, test structure use in integrated circuits, and CMOS technology development. He has also presented tutorials on ESD, latch-up, and transmission line pulse testing at IEEE and ESDA conferences. Robert is an active member of ESDA working groups for device testing standards and the JEDEC latch-up working group. He has been a regular member of the EOS/ESD Symposium technical program committee. Robert served on the ESDA board of directors from 2011 to 2013 and was business unit manager for advanced topics in 2012 and 2013. He is currently serving as vice chair of the human metal model (HMM) and System Level ESD Modeling working groups.
Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.
