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New Joint Standard for Component Level ESD Sensitivity Testing – Charged Device Model

lightening photoThe ESD Association and JEDEC Solid State Technology Association announced the publication of ANSI/ESDA/JEDEC JS-002-2014 for Electrostatic Discharge Sensitivity (ESD) Testing – Charged Device Model (CDM) – Component Level.  The product of a JEDEC/ESDA agreement to produce joint standards in the field of device ESD sensitivity testing, the new standard is intended to replace the existing Charged Device Model ESD standards (JESD22-C101 and ANSI/ESD S5.3.1). A complimentary download of ANSI/ESDA/JEDEC JS-002-2014 may be obtained from or

ANSI/ESDA/JEDEC JS-002 establishes an improved procedure for testing, evaluating and classifying components and microcircuits according to their susceptibility to damage or degradation by exposure to a defined charged device model (CDM) electrostatic discharge (ESD).  ESD can significantly impair the reliability and operation of solid state devices, and accurate test methodologies are critical to the industry as technology advances and device complexity increases.

As was the case with the publication of their first joint ESD standard in 2010 for Human Body Model ESD testing, JEDEC and ESDA expect this harmonized test method for CDM to benefit the industry by eliminating confusion and duplication of effort in the industry..  One key objective for the merger of the previously used test methods was to preserve the JESD22-C101 voltage classifications in the new standard. This has been accomplished in JS-002 with minimal hardware changes required.  We also expect this harmonization will remove any barriers device suppliers may have had to reporting or communicating CDM sensitivity data to their customer in datasheets or other documents.  While it has been known for sometime that CDM is by far the dominant ESD failure cause in production, only a small percentage of datasheets (approximately 10%) currently have this vitally important information compared to over 75% for HBM.   Users of ESD sensitive devices should be asking for this information as part their ESD control program management. “ESDA is delighted that our collaboration with JEDEC has enabled both organizations to serve the industry through the development of joint standards for the ESD testing, and we look forward to continuing our joint efforts to improve ESD test methods and adapt them to new technologies,” said Terry Welsher, President of the ESD Association.

- Partner Content -

VSWR and its Effects on Power Amplifiers

Voltage Standing Wave Ratio results from an impedance mismatch between a source (an amplifier) and a load (test application). This mismatch can influence the performance of the source.

By joining forces to develop JS-001 and JS-002, ESDA and JEDEC have answered the industry call for clarity with regard to test methods for ESD, and we look forward to our continued partnership with ESDA.

John Kelly, President of JEDEC

Photo by yayaempress

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