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Most Important PCB Layer Stack-up Considerations That Achieve Optimal EMC Performance

There are many books and other reference materials available that describe proper printed circuit board (PCB) layer stack-ups to achieve EMC compliance (see References and Further Reading section located at the end of this article for a list of a few of them). The references available cover the gamut from single-layer boards to the number of layers in the teens (multilayer) on a single board and the advantages and disadvantages of each. The level of detail available from the references is well beyond the scope of this article. The intent of this article is to get to the heart of what it takes to achieve optimal EMC performance from a PCB in as few words as possible.

Note: Optimal EMC performance refers to minimal radiation emitted from the board and, conversely, building a board with the least amount of susceptibility to RF fields.

Multilayer Board Objectives

Reference 1 states that for multilayer boards, six objectives should be considered. However, not all are achievable depending on the stack-up assignment chosen. The six objectives are:

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  1. Signal layers are placed adjacent to plane layers.
  2. Signal layers are tightly coupled to adjacent plane layers.
  3. Power and ground layers are closely coupled to each other.
  4. High-speed, high-threat signals are routed between planes on buried layers.
  5. Low reference plane impedance results in reduced common-mode radiation using multiple-ground reference planes.
  6. Critical signals, if routed on more than one layer, are confined to two players adjacent to the same plane.

Old Way of Thinking About and Understanding PCB Layer Stack-ups

Although Reference 1 is probably the best practical book ever written on EMC, it was published in 2009 and may be outdated. Given the higher speed, shorter rise-time, and lower voltage signals, we are now working with the advice given in 2009 (or earlier) that may not apply today. In engineering, it is best not to blindly follow advice or rules of thumb without fully understanding the underlying assumptions and why that advice or rule of thumb was provided.

You may have read about or been taught about the circuit’s point of view, where signals and power require a return path back to the source, where the return path loop area must be minimized. References 1, 3, and 4 also describe how return conduction current travels along the path of least resistance at low propagation speeds (low frequency) and, conversely, how the return conduction current follows the path of least impedance at fast propagation (high frequency).

New Way of Thinking About and Understanding PCB Layer Stack-ups

A better way of solving EMC problems on PCBs is currently being taught. References 5 and 6 present a new way of thinking about achieving optimal EMC performance from a PCB by understanding how digital signals move in circuit boards.

The new way of thinking is that signal and power transient fields travel in the dielectric at near light speed, while the conduction/displacement currents simultaneously flow back to the source at ~1 mm/s. An important concept to wrap your mind around is that signal energy is in the fields, not the copper. The copper acts as a waveguide to move energy from point A to point B on a PCB. For example, references 5 and 6 show how a signal propagates on a microstrip PCB trace and how signal propagation is not through the flow of electrons in copper. The wavefront moves through the dielectric at about 6 in/ns in FR4.

Effect on Layer Stack-up for Optimal EMC Performance

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The effect that this new way of thinking has on how fields propagate is to recognize that in the past, we have allowed power and ground return planes to be placed too far apart for good high-frequency decoupling. The power and ground return planes should be placed 2-3 mils maximum, regardless of whether the stack-up assignment is signals/routed power-reference plane-core-reference plane-signals/routed power or reference plan-signals/routed power-core-signals/routed power-reference plane (four-layer board). For optimal EMC performance on a six-layer board, continue to follow the new way of thinking and place each signal layer adjacent to a return plane and each power plane adjacent to a return plane. Repeat the process/way of thinking if working on board designs with more than six layers.

References and Further Reading

  1. Ott, H., Electromagnetic Compatibility Engineering, Wiley, 2009.
  2. Armstrong, K., EMC for Printed Circuit Boards – Basic and Advanced Design & Layout Techniques, Armstrong/Nutwood UK publication, 2010.
  3. Montrose, M.I., EMC and the Printed Circuit Board – Design, Theory, and Layout Made Simple, IEEE Press, 1999.
  4. Montrose, M.I., Printed Circuit Board Design Techniques – A Handbook for Designers, IEEE Press, 2000.
  5. Wyatt, K., Wyatt Technical Services, LLC, “EMC Essentials – Intensive Course.”
  6. Morrison, R., Fast Circuit Boards – Energy Management, Wiley, 2018.
  7. Bogatin, E., Bogatin’s Practical Guide to Prototype Breadboard and PCB Design, Artech House, 2021.

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