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Modernizing the RJ45 Jack and Plug

Design Modifications Necessary to Achieve Faster Gigabit Data Rates

Today’s high speed internet infrastructure relies heavily on both optical fiber in the long haul networks, and copper channels which are pervasive throughout every corner of the network. Telecommunication networks can greatly increase and expand information to all types of people. For example, businesses need a greater telecommunications network if they plan to expand their company. With the internet, computer, and telephone networks, businesses can allocate their resources efficiently and quickly. The physical layer of these networks are comprised of routers and switches that have printed circuit boards, backplanes, connectors and cable assemblies that transport data that must be truly re-designed for high speed data. Unfortunately, the simple connector and its mating plug/cables usually are the last components thought of to be redesigned to accomplish this task. This results in a connector bottleneck that must be alleviated to realize the ultimate data transmission rates possible.

This article will discuss one of the most prolific connectors in the electrical communication field, the RJ45 connector. Most LAN cables use these connectors, so this connector touches most of our lives every day.

Contrary to popular belief, the reports of the death of copper (and copper connectors) at GHz data transmission rates has been greatly exaggerated. Today’s high speed digital connector designs are supposed to transfer extremely high data rates beyond 28 Gigabits/second (Gbps). However, the problem using today’s present design technologies is transferring higher frequency signals from 1GHz up to 6.5GHz through an RJ45 Interface’s ecological system using only a copper cable media.

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Generally, RJ45 data rates are stated as 10Gbps or less, but in actuality the current magnetically driven RJ45s only transmit data at 6.5Gbps. In fact, when designed specifically for high speed without the concern for cost, RJ45 connectors can be optimized to perform at very high data transmission levels.

This article will discuss such an advanced and patented RJ45 connector along with the test and measurement methodologies required to insure these newly produced connectors exceed all specifications. A vector network analyzer and a bit error rate tester are instruments that must be used in order to measure this advanced performance. The advanced connector design is accomplished by using RF propagation and mitigation principles within the RJ45 interface itself.

It is necessary to integrate new and traditional designs together in order to develop new isolation methods to minimize the measurable impact of EMI/RFI interference, shield effectiveness, cross-talk characteristics, insertion loss, return loss and cable length limits.

The design criteria necessary to achieve the connector design changes were:

  1. Creation of a stripline based LCR circuit within the RJ45 jack;
  2. Incorporate ground plane principles within the RJ45 plug and jack interfaces;
  3. Develop a high performance PTFE based PCB for the RJ45 jack;
  4. Design the RJ45 to be backwards compatible to interface with older transmission circuitry in place today;
  5. Achieve operating frequencies up to 12.75GHz and 25Gbps per pair using a NRZ coding scheme with virtually no bit errors; and
  6. Dramatically reduce the power consumption at the RJ45 plug and jack interfaces.

The general practice of using a wire wound ferrite (aka magnetics) on FR4 boards within an RJ45 jack interface had to be completely redesigned. As each new standard emerged, complex cross-talk and EMI/RFI considerations had to be accommodated in a variety of wide-ranging applications. The magnetic components inside the jack were replaced with a stripline flex circuitry that incorporates increased stitched ground planes. This places the requirements for avalanche diode transient voltage suppression (TVS) back onto the PCB, where they belong.

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It should also be noted that using a stripline-based technology minimizes undesired transient energy effects and eliminates the need to place any physical components onto the PCB. This breakthrough from the standard way of doing data transmission moved the jack and plug interface data transmission speeds up to 12.5GHz. This insures the continued use of copper for higher data rates for many more years to come.

In order to increase data rates for the more demanding NRZ and PAM-4 modulation techniques, some advanced design changes inside the RJ45 connector were required. The signal balance between the pins, wires, and their subsequent connections was improved by lowering the capacitance levels within the jack and plug to only 1pF at each pin interface. This novel topology design is prior to any ASIC cleanup that may be achieved afterwards by the supporting printed circuit board.

Understanding the Basics for Stripline Design

When developing any stripline shape that a small spacing creates a low “L” (inductance) and high “C” (capacitance). Thus the balancing formula to use at this point is: Zo = sqrt L / C; which then allows the stripline layout designer to create a much needed controlled impedance environment.

It is important to remember that the Zo is a function of the signal conductors’ width, plus the length, which in turn is a function of the dielectric constant (Ɛᵣ) of the material surrounding the effected shapes and lines. Figure 1 shows two examples of stripline cross section development.

Figure 1
Figure 1


So what actually is a dielectric constant (aka DK)? The dielectric constant above any stripline PCB trace is simply air, which has a dielectric constant of 1.0008:

  1. The DK below a trace of FR4 PCB material is measured as: 4.16
  2. The DK below a trace of PTFE PCB material is: 1.09

What this indicates is that the higher the DK number, the less likely that the material chosen will be able to achieve frequencies above 1GHz. Inversely the lower the DK number, the more likely frequencies from 1GHz up to 20GHz can be achieved at the PCB level.

Figure 2 demonstrates how the substrate material and adjacent ground planes affect the transmission line of a stripline board by creating virtual, inductors, capacitors and resistors.

Figure 2
Figure 2


In order to produce an effective stripline transmission line circuit within any substrate, the transmission line shape must be sandwiched between two ground planes or closely surrounded on both sides. By doing this, the circuit now has a greater immunity to signal cross talk, greater transient energy mitigation capabilities, and provides much better EMI / EMC control characteristics. But, like any coaxial cable, stripline circuitry is non-dispersive. It does not have an actual cut-off frequency (allowing it to have greater performance at higher frequencies). Different methods can be used to successfully support the center conductor shape, but in all cases the region between the two outer copper plates are to be filled with either a PTFE dielectric material or air.

During the design phase of a stripline circuit it is important to understand that the skin depth is very critical. Mathematically it is inversely proportional to the square root of the frequency limit that is trying to be achieved in the layout.

So, what is the actual meaning of skin depth?

Skin depth is defined as the distance measured across the surface of the center conductor. So, if the skin depth is deeper at the center of the hot conductor or shape, then the current flow across that shape is not limited and flows uniformly throughout the entire cross sectional area of the conductor’s face. To simplify things down a bit here, when a designer is trying his or her best to achieve the frequency design limit, it is very important understand that a proper stripline circuit design requires three conductors (also known as layers to some stripline radar circuitry designers).

The internal conductor which is commonly called the hot conductor has to be evenly sandwiched between two outer conductors, which are called the ground conductors, leaving the hot conductor embedded in an isotropic dielectric constant (“εr”).

Stripline signal path control has to be maintained throughout the entire design; thus it is important to remember that signal return currents always follow the path of least Impedance. When used in high frequency circuits for GHz applications, return currents will follow the path of least inductance. This rule is a finite rule and when neglected in any stripline layout (where low impedance return paths for signal/data transmission are incorrectly laid out), the data stream signals will find a path to couple onto, which is more than likely not the path the designer had in mind.

Figure 3 shows a properly applied signal/transmission path situated between chassis ground planes. This prevents any cross talk or other EMI interference to occur between the signal trace paths throughout the test PCB.

Figure 3
Figure 3


Stripline Signal Trace Control Methodologies

Design rule 101: If everything else is held constant, lower Er materials yield higher impedance traces. This will also ensure faster propagation times as long as the trace widths and trace to ground separation balances are maintained properly. All dielectric material is frequency dependent so, when not applied correctly to a flex material’s centered shape application, the cross talk, and RF noise will increase rather than being reduced, which is just the opposite of what is necessary to increase high speed data transmission rates.

Interestingly enough, if the trace spacing between the ground planes increases, the impedance increases and as a signal trace width increases the trace impedance decreases. Signal traces longer than the critical design length of 1/16 λ in DK must have increased impedance control to prevent return loss due to reflections. Also, if shorter circuit trace paths are applied in the design then any additional impedance control will not be required.

Signal loss or noise control onto a rigid PCB or flex circuit are directly influenced by the molecular structure of the dielectric material used. Therefore, when PTFE dielectric materials are employed, the data rates and high frequency achievable levels become hundreds of times greater than when only FR4 dielectric materials are chosen for GHz transmissions over a copper line.

For stripline development the critical signal line length requirements are the primary function of frequency. So, in this case, it is 1/16th of a wavelength. Simply put, the lower the length in inches by using the proper dielectric material, the higher data rate speeds can be achieved. Figures 4a, 4b, and 4c are examples of the methodologies and the mathematics employed to create properly functioning stripline circuits.

Figures 4a, 4b, and 4c also demonstrate how the physical shape of the centered conductor of a stripline layout actually creates the physical circuit without the actual need for standard components to be positioned onto the circuit board.

Figure 4a
Figure 4a


FIgure 4b
FIgure 4b


Figure 4c
Figure 4c


In most traditional electronic textbooks, the properties of cables and wires are just considered primarily as transmission lines and only briefly is skin effect mentioned. This is usually done without ever exploring any practical PCB related design case studies.  This emphasizes why the connector and plug become extremely important to any data transmission performance.

The critical parameters that tend to be improperly considered in most textbooks today are the capacitance per length, and inductance per length, along with their relationship to the signal’s nominal propagation velocity. The characteristic impedances of the transmission line must be considered as well because standard copper materials have a finite conductance/resistance built into them which are usually not considered beyond their effect upon the D.C. driven low frequency resistance of the cables. This is the primary cause in signal or power losses.

It is not just a jack or a plug that allows the entire cabling system to permit data to travel faster down the shielded copper wires with any category cable. Instead, what becomes a crucial focal point is the mating of the plug and jack, plus their incompatibilities at the very point of wire connectivity within the jack itself.

In Figure 5, the shielded plug and shielded jack assemblies produced by two different manufacturers have been inserted into one another. Please note the physical mating incompatibilities prior to any actual electrical connections have been made.

Figure 5
Figure 5


The problem is that the general user or even the end user at a cloud storage level does not consider the capacitance, resistance, or inductance produced at the internal pins of the jack. These must be taken into account in order to reduce RF signal noise at higher frequencies. This complete disregard and conflict in the design rules by multiple manufacturers over many years has become the primary source of incompatibility issues with cable and connector insertion.

Design features that must be addressed in order to maintain signal and data integrity at the test circuit board level prior to testing are the connector & mating plug design parameters which must be required to follow universally in order to produce a positive change in connectivity are:

  1. A multilayer printed circuit board must be designed using EMI/EMC grounding techniques that are layered upon PTFE based dielectric material;
  2. Positive pin positioning must be maintained upon insertion into the jack by the plug to reduce capacitance;
  3. Twisted shielded pair separation for all conductors plus a properly grounded outer shield layer must be maintained ecologically from the cable to the plug to the connector. Also the drain wire cannot be used as if it were a shield extension;
  4. Line separation via ground isolation in between each transmission line must also be maintained to reduce or eliminate EMI/RFI intrusion. (See Figure 6 as shown).
Figure 6
Figure 6


Shown in Figure 7 are both the tab up (TU) and vertical RJ45, bit error rate and network analyzer test boards in differential mode. These were designed specifically to allow unobstructed signals without any cross talk on the test boards themselves and thus insuring only the unit under test is characterized. This type of test fixture must be maintained so that the proper measurements on either a bit error rate tester or network analyzer can be made. Note the 50 ohm resistor termination at the end of each unused channel are there to avoid reflected signals.

Figure 7
Figure 7


Test and Measurement Techniques

Displayed are the impedance profiles before and after being de-embedded by the automatic fixture removal (AFR) algorithm of the physical layer test system software. This novel de-embedding technique allows the most accurate and simple method of removing unwanted test fixture effects. Normally, the lossy fixtures will degrade the channel performance to the point where the measured impedance of the RJ45 connector is significantly different from the true impedance. The AFR error correction method helped achieve precise impedance profile measurements.

Figure 8: Tab up (TU) RJ45 with stripline flex
Figure 8: Tab up (TU) RJ45 with stripline flex


Figure 9: Time domain differential measurement of the Tab Up stripline RJ45
Figure 9: Time domain differential measurement of the Tab Up stripline RJ45


Figure 10a: Eye diagrams measured before fixture is de-embedded using the AFR algorithm
Figure 10a: Eye diagrams measured before fixture is de-embedded using the AFR algorithm


Figure 10b: Eye diagrams measured after fixture is de-embedded using the AFR algorithm
Figure 10b: Eye diagrams measured after fixture is de-embedded using the AFR algorithm


Figure 11: Eye diagram after fixture de-embedded using the AFR algorithm with a simulated receiver equalization.
Figure 11: Eye diagram after fixture de-embedded using the AFR algorithm with a simulated receiver equalization.


(For further information on AFR, please see the technical library at  Note that the primary Cat 6A cable that was used in all of these tests, remained attached between the test boards during all measurements.

Note: The eye diagrams displayed in Figures 12a and 12b use simulated receiver equalization and transmitter pre-emphasis.

Figure 12a: Shown from left to right, the data rates and their related eye diagrams are:  3.9GBs, 5.0GBs, 10GBs, 12.5GBs
Figure 12a: Shown from left to right, the data rates and their related eye diagrams are: 3.9GBs, 5.0GBs, 10GBs, 12.5GBs


Figure 12b: Shown from left to right the data rates and their related eye diagrams are:  17.5GBs, 8.0GBs, 10GBs, 12.5GBs, 14.0GBs, and 15.0GBs
Figure 12b: Shown from left to right the data rates and their related eye diagrams are: 17.5GBs, 8.0GBs, 10GBs, 12.5GBs, 14.0GBs, and 15.0GBs

So, in order to achieve 17.5GBs at the de-embedded RJ45:

  1. The Cat 6A cable that was connected between the two test fixtures during testing and became the dominant component for loss in the channel due to plug and jack discontinuities;
  2. Physically removing the stripline based RJ45 connectors (both TU and vertical) from their respective test boards became critical to enhancing the quality of the open circuit reflect standard of which was used as a reference for the AFR algorithm to be employed;
  3. Multiple board/cable/connector measurements, were then measured to compare and contrast various de-embedding and equalization optimizations during the testing phase;
  4. 50 ohm terminations on all the unused channels were necessary to minimize multiple reflections, and crosstalk within test fixtures themselves;
  5. Using the AFR portion of the PLTS measurement software for the network analyzer had multiple benefits. These included minimizing reflections in the impedance profile and return loss as shown in the opening of the eye diagrams;
  6. It is to be noted that the frequency point at which the test fixture insertion loss and return loss crossed at was 12.75 GHz (which is included the stripline based RJ45 jack’s test performance).


The data presented in this article is based upon utilizing a stripline technology to provide a path for copper’s future in GHz transmission frequencies. But remember that all of this is provisional upon also paying attention to proper grounding/shielding rules within a cable, removing the magnetics from the design above 1.0GHz, and designing in a compatible ASIC to minimize reflections in the impedance profile/return loss. In addition, using printed circuitry based on a PTFE dielectric material, and using bi-directional high speed avalanche diodes (TVS) for transient surge protection at the base of the connector into the PCB.

All of these proven and tested real time methods will assure that copper can truly achieve high speed data communication data rates that were only considered available through the use of optical cable technologies.

author robinson-brettBrett D. Robinson, Ph.D., is the principle of Robinson’s Engineering Consultants based in Mesa, AZ, and Chief Technical Officer for Sentinel Connector Systems (West). He can be reached at

Resso_HeadShot1Michael Resso is a signal integrity application scientist at Keysight Technologies (formerly known as Agilent Technologies) in Santa Rosa, CA. He can be reached at

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