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Local PCB Layout Tweaks for Improved Signal Integrity When Using ESD Protection Devices

Slight increases in line impedance can significantly improve the SI behavior of high-speed links

High-speed interfaces are essential to satisfy the need for processing massive amounts of data. In all market segments, from consumer and computing to industrial and automotive, the trend is to introduce innovative technologies or to increase the data rate of existing interfaces to reach gigabit speeds. The computing segment usually leads the race for higher data rates. Just recently, the USB standard was extended to support 80Gbps with its latest revision USB 4.2. In automotive ethernet applications, the data rate will increase up to 25Gbps over a single differential pair.

The extremely high functional density of physical layer (PHY) circuits for all these high-speed interfaces usually does not allow robust on-chip protection against electrostatic discharge (ESD). That is why external ESD protection devices are used to fulfill the system’s ESD requirements. Besides the ESD requirements, all high-speed interfaces need to fulfill the requirements on signal integrity (SI). The ESD device itself introduces a discontinuity into the interface and might violate the limits of SI.

In this article, we will show how the SI of high-speed interfaces including an ESD protection device can be improved by modifying the layout of printed circuit boards (PCB).

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Concept

In detail, the ESD device can be seen as a small capacitance. In a single-ended configuration, this ESD device is placed on a transmission line, e.g., a microstrip line (MS) as shown in Figure 1a. In microwave theory, the impedance (Z) of a transmission line is mainly defined as the square root of the ratio of the intrinsic inductance and capacitance (C) per length (L), as follows:

  (1)

This means that the ESD device locally introduces an additional capacitance to the MS’s impedance. This can be clearly seen as an impedance drop in the impedance profile which can be determined by means of time domain reflectometry (TDR, see Figure 1a). Such an impedance drop can potentially violate the SI limits (usually ± 10% of the system impedance which is typically 50Ω and 100Ω for single-ended and differential, respectively).

One highly effective method to overcome this is to modify the impedance of the trace around the ESD protection device. Since the ESD device lowers the impedance due to its capacitance one can locally increase the value of the MS impedance (typically within the limits of 10%) as shown in Figure 1a.

From the microwave theory’s point of view, the increase of the impedance means that trace becomes more “inductive,” which in our case can compensate for the capacitance of the ESD protection device. In the impedance profile, it can be observed that the microstrip line pushes the impedance at the ESD device back to the targeted system impedance, e.g., 50 Ω, as shown in Figure 1b.

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Figure 1: ESD protection in an interface placed on a 50Ohm transmission line. 1a (left) with 50 Ohm impedance, 1b (right) with local 54 Ohm impedance

To verify the theoretical considerations which were presented before, two simulations were performed in Keysight ADS using built-in transmission line models and measured scattering parameters (S-parameters) of a real ESD device. The setups for both cases are shown in Figure 2.

Figure 2: Simulation set-up for the initial and the improved case. For transmission lines build-in models from ADS are used. For ESD protection, device-measured S-parameters are used.

Simulation Results and Implementation on a Real PCB Design

The S-parameters used in this example originate from an ESD protection device with a device capacitance of 0.3 pF that comes in a two-terminal, leadless DFN1006 package, with a pitch of 0.65 mm and body dimensions of 1 mm x 0.6 mm x 0.47 mm. This package is frequently used in gigabit applications with frequencies up to several GHz. The S-parameters are measured via VNA.

Example designs of 50 Ω microstrip lines that can accommodate the aforementioned package are shown in Figures 3a and 3b. Simulating the impedance profile using TDR with a rise time of 100 ps for these components results in the graphs in Figure 3a. It shows an impedance drop down to 43.5 Ω, which is caused by the ESD protection device. This can be a violation of the SI limits for some sophisticated applications such as HDMI.

Based on the concept introduced before, a short section of the transmission lines on both sides of the ESD device is tuned to an impedance of 54 Ω. The resulting microstrip line dimensions are shown in Figure 3b. A simulation of this design yields an improvement of the overall impedance profile as can be seen in Figure 3b. The impedance drop can be successfully reduced from roughly 43.5 to 47 Ω which is typically within the SI requirements.

Figure 3: Results for the initial case (3a, left) and the improved case (3b, right) with adding a 54 microstrip line with the length of 172mil (4.1mm). An improvement of roughly 3.5 Ohms can be observed.

Unfortunately, what sounds like the perfect trick to mitigate the impact of the ESD protection impedance does not come without consequences. The downside is that shifting the PCB trace impedance up for a short section may cause SI problems when the impedance of the PCB deviates from its target due to production spread. Local impedance tuning plus an upward production shift may violate an upper impedance boundary. Thus the length of the modified microstrip line section needs to be made just as long as needed to compensate for the drop that is caused by the ESD protection capacitance.

To find the optimum length, we refer to the impedance equation for a typical transmission line, as shown in Microwave Engineering by Pozar, Fourth Edition, p 148:


   (2)

Here, εeff ≈ (ε + 1) / 2, d is the thickness of the prepreg and W is the width of the transmission line. From this formula, we can further calculate the value for capacitance per length by

where c0 the is the speed of light.

In our specific example, we see that our impedance in the TDR drops down to 43 Ω. The capacitance per length for a 43 Ω microstrip line is 0.14 pF/mm.
With 0.3 pF of added ESD device capacitance, this leads to an equivalent microstrip line length of 2.1 mm (86mil).

We can now take this value to estimate the length of the higher impedance trace which we want to add to compensate for the capacitance. Based on our experience, it is most efficient to take roughly double the length, which is then 4.2 mm (172 mil). As outlined in Figure 3b, the resulting microstrip line has one impedance-adjusted section of the calculated length before the ESD protection footprint and one behind it.

It should be mentioned that the length of the microstrip line section tuned to 54 Ω should not be too short to be efficient but also not too long due to reflections when the added piece of microstrip is in the range of the wavelength. In our case, the wavelength at 7 GHz for a microstrip is roughly 79 4mil (20 mm). We estimated 172 mil, so we are in an acceptable range without expecting any reflections in this frequency range.

In addition, the presented concept works to compensate for capacitive discontinuities which are electrically not too long. It means the dimension of the discontinuity should be <λ/4. This is usually valid for most of the high-speed links just because the dimensions of the ESD devices used for those applications are very small (0603, 0402, or smaller). So, in most cases, we can consider the ESD device much smaller than the frequency range of interest.

Without a doubt, the main advantage of this method is its simple way of implementation. To achieve an increased transmission line impedance, just a slight reduction of trace width is needed. An example is shown in Figure 4 based on a microstrip configuration in FR4 (εr=4.4). In order to realize the intended tuning, the trace width needs to be reduced by roughly 1 mil (0.025 mm). All other parameters can be left untouched. This easy-use fact makes this method very easy to implement and, hence, very effective. There are many tools for calculating the trace impedance which are available to all users for a broad range of uses.

Figure 4: Example of a 50Ohm (4a, left) and 54 Ohm (4b, right) configuration of a microstrip line just by reducing the width of the trace

In addition to the time domain simulation results previously presented, a performance improvement can also be observed in the frequency domain. Looking at the simulated S-parameters, shown in Figure 5, the bandwidth shows an increase up to 7.5 GHz for the IL and RL.

Figure 5: Results for the initial and the improved case in the frequency domain using S-parameters. In 5a (left), the IL is significantly improved up to 7 GHz. In 5b (right), the RL is improved up to 5dB in the range of up to 7.5 GHz.

To focus once again on the length of the additional trace. Figure 6 compares the S-parameters between the initial case and a modified case where the additional trace is too long, which means that it is 800 mil (ca 20 mm) which corresponds roughly to 1λ. The IL is dropping at some frequencies (@4 GHz and 8 GHz) and the RL is increased correspondingly. From the microwave theory point of view, when we increase the length of the high impedance trace, we observe that more reflections stepping into the frequency range of interest decrease the SI performance of the link.

Figure 6: S-parameter for a modified case with a much too long compensation trace. The trace is in the range of the wavelength (800 mil) and the reflections due to the mismatch are now in the frequency range of interest.

Conclusion

In this article, we have shown that slightly increasing the line impedance adjacent to a discontinuity can significantly improve the SI behavior of high-speed links. In a real PCB design, this impedance increase can be achieved by simply narrowing down the trace width which is in most cases quick and easy to implement. The length of the changed line segment can be calculated from the capacitance per length and should be below the quarter wavelength of high frequency of interest. This makes this method very easy to use.

However, it should be mentioned that for some PCB technologies with higher manufacturing tolerances, the impedance range can be violated by introducing this method. In addition, this method works only when the rise time of the TDR signal is not too short. In this case, a rise time of 100 ps was used. For much shorter rise times with greater resolution, this method might deliver expected results. The length of the trace should be not too long which would lead to additional reflections and limiting the link performance.


Andreas Hardock is a Principal Product Application Engineer at Nexperia, with a focus on ESD and EMC issues impacting the automotive domain. He can be reached at andreas.hardock@ nexperia.com.
Martin Pilaski is responsible for worldwide product application support of Nexperia’s bipolar discretes portfolio, with a focus on ESD and EMC for mobile, portable, consumer, and computing applications.
He can be reached at martin.pilaski@ nexperia.com.

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