Let’s Talk About Design for ESD Immunity

Introduction

This brief article is intended for those who may be new to the field of compliance engineering and want a better understanding of process to design products that are immune to electrostatic discharge (ESD) events.  Some individuals may be unsure of where to start the design process or are unfamiliar with the major challenges and issues involved in developing a product that is fully immune to ESD immunity events.  Readers are encouraged to take this information and use it as a springboard for gathering their own knowledge into this very important and often unavoidable subject.

Note:  This article covers design for ESD immunity and not ESD immunity testing.  See reference 1 for a brief article covering ESD testing and the use of ESD simulators.  ESD immunity testing is fully described in standards such as IEC 61000-4-2, MIL-STD-461G CS118, ISO 10605, ANSI C63.16 and RTCA/DO-160.

Timing of Development of an ESD Immune Product

Although not always possible, it’s extremely important to consider design for ESD immunity and ESD protection as part of the up-front, early design work in product development.  At the end of the product development cycle, key elements of the design, including the grounding scheme, chassis design, printed circuit board (PCB) layouts, software/firmware structure and production requirements have already solidified.  It’s much easier, more effective, and less costly if solutions to anticipated ESD problems are implemented at the beginning of the product development cycle while the design is still fluid, rather than added on at the end of the project.  Tackling ESD problems often follows a system-level approach.  Therefore, if the majority of the system is already set in stone, then the most practical solutions available to the designer are fewer, less practical, more complicated and much harder to implement.

Basic Design for ESD Immunity Guidelines

The system-wide approach mentioned above may not be the only way to prevent and mitigate ESD issues.  However, based on experience, it has proven to be the most effective method.  Following this approach, and the guidelines that follow, will ensure any design is capable of meeting its ESD immunity requirements. Keep in mind that not all of the guidelines described in this article can be implemented 100% of the time due to specific design constraints placed on any specific product.  These design constraints vary from product to product and company to company.  It is up to the design engineer to sort out the best combination of methods for achieving ESD immunity of each specific product and specific situation. As an example, a design constraint may be that a customer has already specified only unshielded cables can be used.  Therefore, you won’t be able to utilize shielded cables in your solution that ensure the product is immune to ESD events.  Another design constraint might be that a metal chassis must be used.  In this situation, you will have to find a way to control the path the ESD current takes to prevent it from getting inside the enclosure.

Prevent Entry of Discharge

The first part of system-level design for ESD is to prevent entry of the ESD discharge inside the enclosure.  It’s best, but not always possible, to prevent an ESD event from occurring in the first place.  This should be an easy task to accomplish if your product is contained in a non-metallic/plastic enclosure.

For those who do not have the luxury of a plastic enclosure, you will need to spend some time thinking about other methods to control how your product will respond to an ESD event and how to best control the path the ESD current takes so that it doesn’t enter the enclosure.

Any unshielded cables that enter or exit your device should contain transient protectors on each conductor. Devices such as transient voltage suppressor diodes (TVSs) placed on each line are useful in diverting any energy away from critical circuits. When placing these devices, be sure to follow proper grounding techniques and avoid using long lead lengths for connections.  Lead wires have inductance of ~ 10 nH/cm (25 nH/in) and if made too long become essentially open circuits to the ESD pulse.  I’ve gotten bitten more times than I’d like to admit by allowing lead wires that were too long for the application and allowed the ESD pulse to bypass the protection elements.

Mount the suppressors or any other filtering devices (such as capacitors) as close as possible to cable entry point to the enclosure to help ensure the ESD current is diverted to the metal enclosure and away from critical circuits located within it. It is critical that the ESD current path is diverted away long before it has a chance to cause any upset or damage to critical circuits contained further within the enclosure.

If possible, use cables that are properly shielded.  Use a metal backshell connector and ensure that it forms a complete 360° connection around the internal cable shield.  Complete contact between shield and enclosure is essential.  Avoid using the infamous “pigtail” type of cable shield connection.  At the frequency of the typical ESD pulse (~ 300 MHz; see note below) the pigtail connection contains way too much inductance (~10 nH/cm) to be effective.

Note: The typical ESD pulse has a risetime (t_r) in nanoseconds which equates to EMI in the frequency domain of hundreds of MHz (f_(MHz) = 1/πt_r).

For the enclosure itself, ensure that any slots or seams do not destroy ESD shielding by limiting their longest dimension to 1/20^th of a wavelength at highest frequency of concern (~ 300 MHz).  A rule of thumb is that a slot less than 5 cm (2 in.) will provide roughly 20 dB of attenuation, and a slot less than 5mm (0.2 in.) will provide about 40 dB. If required, seal slots and seams with conductive gasket material.

To achieve good ESD immunity using a metal or metalized enclosure, only 20 to 40 dB of shielding is required.  Very often thin shielding material works well enough.  Aluminum foil provides greater than 100 dB attenuation, metal coatings provide at least 40 dB, and vacuum plating/electroless deposition are good for around 80 dB at the frequency of the ESD pulse.

Harden Sensitive Circuits

The next part of the system-level approach is to look for ways to provide ESD protection and harden sensitive circuits contained within the product. Place filters on critical internal lines such as resets, interrupts, and control lines.  A typical low-pass filter used in this application consists of an RC network of 50 to 100Ω resistance and 100 to 1000 pF capacitance.  A properly specified ferrite bead can be used in place of the resistor.   Avoid direct connections from any integrated-circuits to exposed external points.  ESD will find its way to these weak points and ruin your day!

Keep Loop Areas Small

Consider using multilayer printed circuit boards to control loop areas.  Multilayer PCBs are tens to hundreds of times more immune to ESD events than two-layer boards.  The larger loop areas easily developed when placing traces onto two-layer boards act as receiving antennas to the fields created by ESD events.  When the planes on a multilayer board are stacked correctly, it’s possible to utilize the opposing currents induced in a nearby plane to cancel the fields from the plane or trace subjected to an ESD event.

Write Transient Hardened Software/Firmware

Plan for the unexpected and include noise-tolerant software/firmware (SW/FW) as part of your design for ESD immunity plan.  This is one area those of us who are more hardware-centric often forget to employ. Hardware engineers are more inclined to try and fix every problem with hardware and ignore anything SW/FW related. Although writing transient hardened SW/FW won’t work on issues where there is ESD damage, possible use of SW/FW as a viable ESD protection method should not be overlooked. As such, we need to assume that sooner or later ESD will upset the system and some type of recovery is necessary.  The goal of the recovery process should be graceful degradation, not total system lockup and where turning power completely off and back on is required to restore correct operation.  Part of this graceful recovery involves development of “watchdog” routines that restart a product should their processor get hung-up.

Conclusion

A system-level design for immunity process has been outlined above.  Many of the design for ESD immunity techniques presented are identical to those used to provide increased immunity to other forms transient events, such as electrical fast transient burst and radiated and conducted RF immunity.  If utilized correctly, these same design elements help the product to pass both radiated and conducted RF emissions testing. Based on the above, any further research and study committed to the subject of design for ESD immunity is well worth the extra time and effort put into it.

References

1. In Compliance Magazine. (2018, February 5). What Every Electronics Engineer Needs to Know About: ESD Simulators Retrieved from https://incompliancemag.com/article/esd-simulators
2. https://webstore.iec.ch/publication/4189, IEC 61000-4-2:2008 Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test.
3. Ott, Electromagnetic Compatibility Engineering, Wiley, 2009.
4. http://www.mddionline.com/blog/devicetalk/what-you-need-know-iec-60601-1-2-4th-edition-02-22-17, What You Need to Know: IEC 60601-1-2 4th Edition
5. Mardiguian, Electrostatic Discharge – Understand, Simulate and Fix ESD Problems, Interference Control Technologies, Inc., 1986.
6. Wyatt & Jost, Electromagnetic Compatibility Pocket Guide, Scitech Publishing, 2013.
7. Boxleitner, Electrostatic Discharge and Electronic Equipment – A Practical Guide for Designing to Prevent ESD Problems, IEEE Press, 1988.
8. André & Wyatt, EMI Troubleshooting Cookbook for Product Designers, Scitech Publishing, 2014.
9. SEMTECH Corporation, SMDA05 through SMDA24 Unidirectional TVS Array for Protection of Four Lines, 2005.
10. Armstrong, Design Techniques for EMC – Part 2, Cables and Connectors, http://www.compliance-club.com/archive/keitharmstrong/design_techniques2.html
11. Liang, Design considerations for system-level ESD circuit protection, Texas Instruments Incorporated, 2012.
12. ON Semiconductor, ESD7016/D, Low Capacitance ESD Protection USB3.0, 2013.
13. Montrose, Printed Circuit Board Design Techniques for EMC Compliance – A Handbook for Designers, 2^nd Edition, 2000.