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Latch-up Qualification

Question

All my products pass latch-up qualification according to latest JEDEC JESD78E release. Nevertheless, products are returned showing typical latch-up-like failures. Is it possible that latch-up is caused by transients not covered in JEDEC JESD78E? How can I characterize the latch-up robustness of my product against fast transients?

Answer

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The answer to the first part of the question is rather simple: Yes, transients can cause latch-up and these transients are typically not covered by JEDEC JESD78E. To answer the question in more detail, one has to look into JESD78E first and the dynamic behavior of the trigger pulses applied to the pin of a device-under-test in an attempt to trigger latch-up. For a positive voltage pulse applied to any supply (“Vsupply test”), the rise time of the voltage pulse is 5 micro seconds or larger, for a positive or negative current pulse injected to any signal pin (“Itest”), the rise time is larger than 1 micro second. In comparison to a typical pulse of an electrostatic discharge (10 nanoseconds and shorter) or a lot of other disturbances in the system, those rise time are very long. For this reason, JESD78E is often called “static latch-up test”.

Sure, JESD78 is an essential qualification procedure for all products and there is hardly any modern integrated circuit on the market which has not been qualified according to JESD78. Qualifying a product according to JESD78 ensures product reliability and avoids field returns. The success of JESD78 in detecting latch-up, advances in the understanding of latch-up, and improved design techniques has made latch-up a relatively rare failure mechanism in the field.

However, it is well known that products can be more susceptible to fast transients than to the “static” pulses defined in JESD78. Products might show latch-up failures although the products do not show latch-up sensitivity when tested with JESD78. Often (very) fast transients have been proven to trigger latch-up. This kind of latch-up is called transient induced latch-up, commonly known as “transient latch-up” (TLU).

Since more than twenty years, Working Group (WG5.4) of the ESD Association is addressing TLU. As JESD78 is unable to detect TLU and finally prevent products from failing due to TLU, there was a strong request from the industry facing TLU threats to define a TLU characterization method. A first attempt at a transient latch-up test method was released in 2008. A stress pulse was defined with a negative going rectangular pulse applied to the power supply. This stress pulse was successful in reproducing latch-up discovered during failure analysis of an entire class of field failures experienced by one manufacturer and this was the main motivation for writing ANSI/ESD SP5.4.

However, there are many more possible latch-up trigger events than just a negative going voltage surge at the power supply. Obviously, fast transients applied to external ports might be critical, examples are ESD system level stress pulses (e.g., IEC 61000-4-2) or cable discharge events (CDEs). In Technical Report (TR5.4-04-13), the ESDA WG summarizes TLU events. Seventeen typical TLU events in five classes of business applications are discussed in this TR, showing clearly that TLU is a real risk for today’s integrated circuits. Typical stress pules triggering TLU have been ESD system level events, customer-specific stress and reliability tests which try to reproduce critical operating conditions, but also stress pulses occurring during “normal” operation, e.g., disconnect of speaker or functional testing of a SimCard. There is a huge variety of different transient stress pulses that are thinkable – and none of the above mentioned seventeen examples have the same trigger pulse.

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Of course, all seventeen products discussed in TR5.4-04-13 have passed successfully the “static” latch-up qualification according to JESD78. So, in fact JESD78 is not sensitive to latch-up triggered by transients and cannot guarantee product reliability against fast transients. This confirms the assumption in the question that besides passing JESD78, products might be susceptible against TLU. The good news is that typically only a very few pins on a product are exposed to fast transients with a fast rise time and a critical voltage/current amplitude. In contrast to JESD78 in which basically all supplies and all signal pins must be characterized, TLU characterization typically can be limited to a few critical pins only.

The answer to the second part of the question is much more complex. Actually, it was a matter of discussion for nearly one decade in the latch-up community and also in the ESDA WG5.4.

As mentioned before, JESD78 standard qualification is not capable to reproduce even one of the seventeen examples. In four products, latch-up vulnerability would have been detected if JESD78E would have been applied with increased stress levels and compliance values, going far beyond JESD78E. Going beyond the limits in JESD78E can potentially cause problems with permanent physical damages due to electrical overstress. And it does not solve the problem of characterizing the remaining 13 products for which JESD78 would not at all identify any latch-up weakness against transients. Short note: None of the seventeen TLU events could be reproduced with the method described in ANSI/ESD SP5.4. This and the fact that test equipment is not commercially available was the reason to re-designate the Standard Practice to a Technical Report.

In order to cover a broad range of latch-up threats by experimental characterization, a new approach is required which is currently worked on in a new Standard Practice on TLU. The new approach allows the characterization of products with any kind of application-specific stress in an application-specific environment. However, as a slight drawback, the approach requires some knowledge on the threat in the field for a meaningful and sensitive product characterization. There are two types of “standard triggers” recommended in the SP, however, these triggers can hardly cover all possible TLU events. As an example, the trigger pulses defined in the SP are square pulses, but there might be bipolar trigger events which are more critical for the application. As a consequence, as more you know about your application the more meaningful can be the characterization approach.

Although the trigger of the TLU characterization is not strictly defined in the document, the methodology described in the SP advances the state-of-the-art of TLU characterization significantly. For a typical latch-up characterization, pre-conditioning of the device, a stress pulse to the device and a latch-up detection mechanism are required. The document defines all of the components but allows application-specific modifications for all of the components. However, the verification of all components to ensure that the characterization yields reliable and correct results is always the same and it is the corner stone in the document. If a characterization study with a certain trigger pulse does not show a latch-up event, it must be guaranteed that the set-up would be capable to detect such a latch-up event.

While it is rather simple to verify that the product-under-test is in the desired logical state and that the defined pulse form is actually applied to the pin (that may be an internal pin of the package of the product, but also a pin at an external port – depending on the application), the verification of the power-supply response time is not straight-forward, but is crucial. With trigger pulses as short as a few tens of nanoseconds, the response time of the power supply must be fast enough to provide voltage and current under certain load conditions which is required to retain the latched state – at least, in the experimental characterization set-up the response time must be as fast as in the real application, e.g., the battery in a mobile application. On the other hand, it must be guaranteed that there is a current limiting capability (“current compliance”) included in the power-supply system to avoid permanent physical damages due to current overstress.

The simplest methodology to perform TLU characterization is to characterize the product in the target application, e.g., while running on an application (test) board. This avoids most of the problem with the power-up and pre-conditioning of the product, and in many cases the current consumption of the battery or the external power supply can be monitored accurately enough. There is even no need to characterize the response time of the system as it is (close to) the real system. Stress pulses can typically be easily applied to ports or internal pins, depending on the real threat.

However, often it is desirable to characterize products in an early stage in which typically application boards are not yet available. Or only sub-circuits should be characterized. In these situations, a set-up has to be developed and characterized. Obviously, as more complex is the integrated circuit larger is the required experimental effort. Each additional power supply on the integrated circuit adds another power supply on the experimental set-up which must be monitored and verified. Vectoring can add another level of complexity.

Depending on the characterization task and the application, you might consider to use a commercially available latch-up tester which sometimes could be used for TLU characterization, if the trigger pulse shape of the commercial system is close to the real-world event and if it is verified that the power-supply system responds fast enough. As soon as the Standard Practice of the ESDA is released in 2018 one can hope for more commercial TLU test systems.

For simple TLU characterization tasks, say for only one pin to be stressed and product which does not need vectoring to bring it in the latch-up sensitive state, the set-up consists of a few components which typically are available in any lab. A photo of a simple self-made board to characterize the latch-up susceptibility of a power supply is shown in Figure 1. It consists of a current transducer and a fast scope (1 GHz or faster) to monitor the current of the power supply before, during, and after the stress pulse. A solid-state pulse source delivers rectangular stress pulse with 7 ns rise time and variable pulse length. The DC power is supplied by a simple lab power supply, protected by a diode against the TLU stress pulses.

Instead of the device-under-test, a verification circuit can be connected to the characterization board. The verification circuit can be as simple as a relay used in ESD applications and a series resistor which simulates a fast load change from high-ohmic to a very low resistor defined by the application (Figure 2). The response time between switching the relay, i.e., changing the load from high-ohmic to low-ohmic, and the delivery of the required current across the shunt which mimics the device-under-test is captured by a fast oscilloscope.

To sum up: Yes, TLU exists and it’s a real threat! And, yes, you can perform TLU characterization – but the experimental work requires some effort to ensure meaningful results. For a detailed description of the stress and verification methodology, a new Standard Practice of the ESDA WG5.4 will be issued soon. Stay tuned and visit www.esda.org!

References

  1. JESD78E “IC Latch-up Test”, JEDEC, April 2016, www.jedec.org.
  2. ESD TR5.4-04-13, Technical Report “Transient Latch-Up Testing”, ESD Association, Rome, NY, April 2013.
  3. ESD TR5.4-03-11, Technical Report “Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits; Transient Latch-up Testing – Component Level; Supply Transient Stimulation”, ESD Association, Rome, NY, October 2011 (revision and re-designation of ANSI/ESD SP5.4-2008)., www.esda.org.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds  international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

Wolfgang Stadler received his diploma degree in physics in 1991 and in 1995 the PhD degree from the Physics Department of the Technical University Munich. 1995 he joined the semiconductor division of Siemens, which became Infineon Technologies in 1999. His focus was on development of ESD-protection concepts in CMOS technologies and on innovative ESD topics. In this role he was coordinator of several European and German ESD funding projects. Since 2003 he was responsible for the measurement characterization of I/O cells and PHYs.

2011 he joined Intel Mobile Communications (IMC) which is now Intel Deutschland GmbH. He is responsible for ESD/latch-up testing and qualification, for ESD control programs, and ESD risk assessment and fab support.

Wolfgang holds several patents in ESD-related topics. He is author or co-author of more than 100 technical papers and has co-authored a book on ESD simulation. He received several Best Paper Awards and gives regularly courses on ESD device testing, ESD qualification, and ESD control measures (e.g., TR53 ESD Technician Certification).  He is an active member of the EOS/ESD Association (ESDA) working groups related to device and system testing, ESD control, and process assessment. He is also member of STDCOM and TAS of the ESDA.  Since 2011 he has been the committee chair of the ESDA Working Group 5.4 “Transient Latch-up” and since 2013 he has been co-chairing the ESDA Working Group 17 “Process Assessment”. He has been elected to serve on the Board of Directors of the ESD Association for 2014–2019; 2015 he was appointed as Education Business Unit Manager of the ESDA. Since 2015 he has acting as the president of the German ESD FORUM e.V.

He can be reached at wolfgang.stadler@intel.com.

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