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Latch-up Electronic Design Automation Checks

Circuit design reliability verification in Integrated Circuit (IC) design is extremely challenging. Leading edge products have many supply domains and voltage levels for different functional blocks like RF, digital, and high voltage, making ESD and latch-up checking a complex and error prone task. Relying on manual verification alone poses a significant risk of missing design flaws, which can be very costly during manufacturing and in the field. Consequently, automated ESD and latch-up checking is highly desired in today’s design flow.

EDA tools for ESD and latch-up verification tools have significantly matured in the past few years. ESD Association’s EDA working group continues working on the subject. While initially the focus was primarily on ESD [1], in the recent years it shifted to the EDA tools for latch-up. This article highlights some of the aspects of latch-up EDA verification flow.

While the physical phenomena leading to latchup are well recognized in the industry [2], verification methods to identify these risks have not been widely discussed. When considering specific latchup verification flows it is important to understand the benefits and limitations of different methodologies available for verification. While some simulation based solutions consider substrate resistance, detailed analysis of this type of failure mechanism is best left to TCAD and SPICE based simulation environments.

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Scalable, full-chip solutions that holistically consider the voltages used within the layout of the design and focus verification on the context of how devices and physical design elements interact are the most effective at identifying “at risk” areas of the design, while providing a cohesive debugging environment. These flows can be leveraged at full-chip levels of the design with sign-off rules and constraints.

In a typical latch-up verification flow external ports must be defined first. This information is critical to find hot diffusions that could become part of the latching parasitic thyristor. External ports could be defined semi-automatically using pin text information in the existing layout along with the passivation opening or other layers to uniquely identify pads. Hot diffusions could be also identified by manually placed marker layers which are then cross checked by connectivity EDA tools. These tools ensure that all diffusions either directly connected to the pad or through a device that can provide a high current conducting path (e.g., small resistors, large switches, etc.) are properly marked. Since I/O pads on one hand, and power and ground pads on the other hand pose different latchup risks, they are distinguished either by following an established pin naming convention or by grouping different pin types into a dedicated file with pin definition information, which in turn is used as an input to an EDA verification tool. The same pin definition file can also contain voltage information which is further used to assess the severity of latchup risk.

Next, latchup prevention methods implemented in layout must be recognized. For example, adding guard rings to collect injected carriers significantly reduces the risk of latchup. Recognizing guard rings in layout either with the aid of dedicated marker layers or automatically by detecting closed shape diffusions is an important part of latchup prevention verification methods. The width of the guard ring plays an important role in defining the efficiency of carrier collection: wider guard rings have stronger collection efficacy, such that the escaping current fraction reduces. Therefore, once the guard ring is recognized, it is checked to ensure compliance with minimum width requirements.

However, the addition of guard rings may not be sufficient to completely prevent latchup. Even if surrounded by guard rings, a parasitic thyristor adjacent to a strong injection source may still be vulnerable to latchup. Therefore, after identifying thyristors by detecting nearby n and p diffusions and wells, an EDA tool analyzes this risk by extracting two layout parameters: the Anode-to-Cathode distance dac and the distance from thyristor to hot diffusion dhd, as shown in Figure 1 [3]. In this figure the layout contains an n+ diffusion connected to pad and a parasitic thyristor at a distance < dhd’. The thyristor is built with an Anode (PMOS) and two Cathodes (grounded n-well and n+/p-well) placed at a distance < dac. The Cathodes are at a lower potential than the Anode. Thus, two parasitic thyristors are built: p+/n-well/p-well/n+ and p+/n-well/p-well/n-well.

Figure 1: EDA method to identify latchup. The dashed lines indicate the distances dac’ and dhd’ at which EDA tool checks for the presence of the parasitic thyristors in layout.
Figure 1: EDA method to identify latchup. The dashed lines indicate the distances dac’ and dhd’ at which EDA tool checks for the presence of the parasitic thyristors in layout.


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A reliable EDA tool must consider the type of hot-diffusion which injects the current [4]. If electrons are injected into the high-Ohmic p-substrate, they can diffuse long distances. When holes are injected, they flow Ohmically in the bulk by drifting to nearby substrate contacts. Due to the transport difference between electrons and holes, the distance dhd around hot p-diffusion at which the EDA tool should check for parasitic thyristors should be much smaller than for hot n-diffusion. Minimum distances dac’ and dhd can be extracted from the measurements or TCAD simulations and compared to the ones in layout. Identifying distances dac and dhd in layout allows flagging and eliminating the worst-case parasitic thyristors. An example of an algorithm for identifying sensitive parasitic thyristors is shown in Figure 2.

Figure 2: Methodology for sensitive parasitic thyristor identification.
Figure 2: Methodology for sensitive parasitic thyristor identification.


Additional details on the proposed Latch-up EDA verification flow could be found in the ESDA Technical Report, which will be released and available for free download at by the end of the year. At the time of writing the ESDA EDA Working Group consisted of the following members: Michael Khazhinsky (Silicon Labs), David Alvarez (Infineon), Norman Chang (Ansys), Krzysztof Domanski (Intel), Eleonora Gevinti (ST Microelectronics), Harald Gossner (Intel), Matt Hogan (Mentor Graphics), Michael Laube (ZMDI), Chien-Hsin Lee (GLOBALFOUNDRIES), Peter Koeppen (ESD Unlimited), Natarajan Mahadeva Iyer (GLOBALFOUNDRIES), Mujahid Muhammad (GLOBALFOUNDRIES), Andy Noiret (Micronas), Guido Quax (NXP), Wolfgang Reinprecht (AMS), Scott Ruth (NXP), Karthik Srinivasan (Ansys), Nitesh Trivedi (Infineon), Vladislav Vashchenko (Maxim), Wenjiang Zeng (Magwel), Paul Zhou (Analog Devices).


  1. M. Khazhinsky, et al, “ESD Electronic Design Automation Checks,” ESDA Technical Report ESD TR18.0-01-14, 2014.
  2. R. Troutman, Latchup in CMOS Technology: The Problem and Its Cure, Kluwer Academic Publishers, NY, 1986.
  3. M. Khazhinsky, et al, “EDA Approaches in Identifying Latchup Risks,” EOS/ESD Symp. Proc., 2016, pp. 1-10.
  4. K. Domanski, et al, “External (Transient) Latchup Phenomenon Investigated by Optical Mapping (TIM) Technique,” EOS/ESD Symp. Proc., 2007, pp. 1-10.


author_khazhinski-michaelMichael G. Khazhinsky is currently an ESD engineer/designer at Silicon Labs in Austin, Texas. Prior to joining Silicon Labs, he worked at Motorola and Freescale Semiconductors where he was in charge of the TCAD development and ESD/latch-up protection solutions for emerging process technologies, with a focus on ESD-EDA. Michael has M.S.E.E. and M.S. Physics from the Moscow State Institute of Electronic Engineering, and Ph.D. in Physics from Western Michigan University. Michael served as a member of the IRPS, IPFA and EOS/ESD Symposium Technical Program Committees, as well as a Workshop Chair, Technical Program Chair, Vice General Chair and General Chair of EOS/ESD Symposium. He currently serves on the Technical Program Committees of 2018 International Reliability Physics Symposium and 2017 EOS/ESD Symposium. Michael co-authored over 50 papers and gave a number of invited talks on ESD, EDA, process/device TCAD, and photonic crystals. He was a co-recipient of six EOS/ESD Symposium and SOI Symposium best paper and best presentation awards. Michael currently holds seventeen patents on ESD design, with additional patents pending. Michael is a senior member of IEEE and an elected director of EOS/ESD Association, Inc.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds  international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

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