Keysight Technologies, Inc. announced the development of a STT-MRAM test solution based on collaboration with Tohoku University, Center for Innovative Integrated Electronic Systems (CIES) STT-MRAM (spin-transfer torque magnetoresistive random-access memory) activities. The solution is designed for testing STT-MRAM devices that are used in super-low-power electronic systems, such as electronic appliances, where it is necessary to reduce carbon emissions.
“We are delighted that our collaborative research has resulted in a successful outcome with Keysight and believe it will contribute to further advancements in STT-MRAM research worldwide,” said Prof. Tetsuo Endoh, professor of the Graduate School of Engineering, Tohoku University and director of the Center for Innovative Integrated Electronic Systems. “As one of seven areas of focus for the CIES research consortium, our goal is to create innovative core technologies for substantial energy savings in integrated electronic devices. This R&D project of the STT-MRAM is intended to develop non-volatile working memory for manufacturing technologies that will contribute to super-low-power electronic systems, which is crucial for a low-carbon society with low-power electronic appliances.”
“As the result of work with Tohoku University, Center for Integrated Electronic Systems, Keysight will launch the STT-MRAM test solution in early 2016,” said Masaki Yamamoto, vice president and general manager of Keysight’s Hachioji Semiconductor Test Division. “Our collaboration with CIES is key for us to develop the STT-MRAM test solution that addresses the various challenges facing the industry’s need for low-power electronic systems.”
