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Impact from IC On-Chip Protection Design on EOS

A Comprehensive Approach Can Reduce EOS-Related Failures

It is commonly understood that on-chip ESD protection is essential to meet the human body model (HBM) and charged device model (CDM) ESD stress reliability requirements for product qualification. The current minimum safe levels as determined by the Industry Council on ESD Target Levels (with much acceptance in the IC industry) are 1 kV for HBM and 250 V for CDM, with good ESD design practice in established technologies giving higher levels to ensure better margins.

While this is ideal, there could be some issues where excessive ESD design levels could cause the well-designed ESD circuits to carry overcurrent for a longer time, making them vulnerable to longer duration transient induced EOS events and unexpected damage. In a similar vein, design to handle overcurrent from latch-up events can also have some impact on EOS if proper rules are not followed.

This article briefly reviews these issues to illustrate that robust ESD protection does not guarantee the IC designs are protected against unintended EOS effects. It also summarizes the various IC design applications and the corresponding ESD design methods that should illustrate any unwarranted EOS damage scenarios.

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The ESD Design Window

First, it is imperative to establish that ESD protection design is strictly for achieving the optimum circuit that can protect for the desired component-level HBM and CDM target levels while not having any negative impact on functionality and/or IC pin reliability associated with gate oxide, junction, or interconnect damage. This ESD operating region is known as the “design window” and is shown in Figure 1.

Figure 1: Typical design window for ESD protection strategy

Any ESD design is bounded by IC operating region, IC reliability region, and the thermal effects defined by the protection clamp. The designer thus chooses the appropriate ESD devices, circuit devices and includes any limiting resistance that can achieve this goal. The trigger voltage (Vt1) of the protection device defines the level at which it is designed to be turned on; holding voltage (VHold) after trigger refers to the clamping level that should be above the application voltage. Finally, It2 refers to the ESD failure current level.

The choices for the commonly used protection devices in Figure 1 are:

  1. As denoted by the blue curves (1A or 1B) an NMOS transistor that goes into bipolar breakdown (npn) at a trigger point Vt1, and snaps back into a holding voltage known as VHold, and protects up to a failure current IESD that corresponds to the ESD target level. (It2, Vt2) refers to the thermal dissipation point where the protection device can burn out and thus this It2 must be greater than the IESD target current level (for example, 1 Amp for target 1.5 kV HBM). If the protection device’s on-resistance (Ron) is too high then Vt2 could also reach the reliability voltage limit. The clamp must trigger effectively such that its voltage buildup does not exceed the gate oxide breakdown (BVox) or the transistor breakdown voltage. The VHold for the transistor is designed so it has some margin to the operation voltage, as in curve 1A. In contrast, in the case where the snapback device with VHold is less than the operating voltage (curve 1B) there is risk for EOS damage.
  2. A second choice in Figure 1 could also be a non-snapback design where the clamp tuns on and conducts the current as shown by the red curve 2. There are both devices and circuit techniques that can be applied to a traditional snapback device to produce this behavior.
  3. An alternate choice is a pnpn device that triggers at a similar Vt1 but has a much lower VHold (at or lower VHold than shown in curve 1B, and hence care is taken so that it does not accidentally trigger during circuit operation). This pnpn device is much more dangerous if placed on the VDD pin since accidental or unintended trigger is strongly possible. In essence, the ESD designer is focused only on the ESD cell and protection path through the component. The ESD advantages of having a lower VHold bring an EOS risk as a trade-off: if the ESD cell is triggered during normal operation, there is a high risk that the ESD cell cannot be turned off, and will conduct current for a much longer time duration than for which it was designed.

Although in general the design of ESD protection is not meant to protect against EOS events, the IC design style of ESD protection with the above-mentioned devices can indeed influence the rate of failures returned resulting from EOS damage, depending on the particular application and operating environment. Figure 2 illustrates two different snapback devices where device 1 is relatively safe compared to design with device 2. The increased EOS risk for device 2 comes from the VHold parameter being below the maximum allowed VDD.

Figure 2: Snapback design to avoid EOS damage

Latch-up and EOS

As mentioned, the pnpn devices can be more problematic for EOS if proper precautions are not followed. Figure 3 illustrates this EOS-prone ESD design operation. This type of device must either have VHold above Vdd or IHold (current needed to keep it in latchup mode) to be higher than the supply Idd current. There are design methods to achieve this so to safeguard against accidental latch-up causing EOS damage. EOS damage has been observed in the case of wrong protection device type like the pnpn placed on power supply pins.

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Figure 3: PNPN ESD protection device design operation showing vulnerability to EOS

Even if the designer takes care with good faith, problems can arise if they are not typically consulted by OEMs concerning actual voltage spike levels in the application. So, in some unexpected cases it can lead to EOS damage. Also, in addition, some design styles involving the trigger and holding voltages can have more of a system-wide impact. Therefore, the designers can only protect against those events possibly resulting from the application requirements customers specify to them.

During latch-up reliability testing according to JEDEC latch-up specification (JESD78), EOS damage could occur at the IO pin if certain conditions are not understood. If the IO pin has high input impedance, the voltage (when current is injected to test for latch-up) can build-up high enough to cause junction breakdown damage in an unintended path before the required latch-up limit for testing is achieved. This can create unnecessary EOS damage causing some customer misunderstanding. JEDEC JESD78 test methodology is being better described in an upcoming revision of the document to avoid such false assessment.

High Speed Designs

Instead of clamping devices at the IO pins, a commonly used design style (see Figure 4) for large groups of digital IO rings is “rail clamp” VDD protection devices where the MOS protection devices operate in the “normal operating” linear and saturation regions with no bipolar snapback of the device during ESD event conduction. It involves an active MOSFET as the rail clamp device between VDD and VSS with its characteristics shown by the red curve in Figure 1. Even in these cases, EOS damage can be an issue if the design does not properly address certain scenarios. For instance, during normal application the “dv/dt” slew rate from IO transitions seen on the power supply can potentially trigger this device into a current conduction mode.

Figure 4: Non-snapback Rail Clamp for ESD protection strategy

A second consideration is the increasing number of high-speed applications that demand advanced technologies. In general, tuning process technology to mitigate unexpected EOS damage from ESD designs is not an option, because the technology is optimized for the IC applications, speed performance and product specification needs. The ESD design comes during technology characterization and matures after the technology has been well established. Thus, any EOS issues arising from specific ESD protection design methods are addressed by either the ESD designer or the IO designer, and sometimes both.

System On Chip Designs

Another aspect comes from system on chip (SOC) designs using multiple power supply voltage levels. Power sequencing in these scenarios often becomes an issue with any internal diodes that accidentally trigger. These diodes can draw significant power during the sequencing transition leading to EOS damage. The more complex the design of a chip (especially SoC with multiple power domains), the more possible that unintended parasitic paths will exist. Unless careful design techniques are followed, returns exhibiting EOS damage could result. Therefore, the SOC ESD protection design must take this into account.

High Voltage versus Low Voltage ESD Designs

One might think that the lower the application voltage, the more sensitive the devices would be for both ESD and EOS issues. On the contrary, low voltage devices can be safely designed for ESD if careful strategies are followed in protecting the thin gate oxides and the transistor lower junction breakdown voltages. The only exception might be reduced ESD target levels because of high speed applications. Once designed for ESD their EOS issues are relatively less common.

On the other hand, high voltage applications often use SCR-type protection devices. Although these devices provide higher ESD protection levels, at the same time they often have a narrower design window (less overhead between maximum operating voltage and IC Breakdown region) and almost always have VHold much lower than the maximum operating voltage. Triggering of these devices under non-ESD conditions can lead to EOS incidents.

Another aspect to consider is that protection designs using high voltage devices have increased power dissipation in the turn-on mode compared to those using low voltage devices. As such, when the device fails to protect or when the ESD device itself fails, considerably more energy is available to cause material damage in the failed region. There has been some correlation noted between EOS damage and the operating voltage or environment the devices are designed into. There are some design recommendations to mitigate these scenarios [1].

Absolute Maximum Voltage (AMR) and EOS

As noted in the Industry Council’s white paper on EOS [1], following the AMR guidelines is critical to avoiding EOS damage. The ESD protection device might exceed AMR but this is only during the brief trigger transient (within the ESD operation timing duration) and no harm is done. But in the case of longer duration application voltage, exceeding AMR is dangerous.

It should, however, be cautioned that further technology advances with thinner gate dielectrics and novel transistor process technologies will reduce breakdown voltages and continue to shrink design windows. This reduction in breakdown voltage translates directly into reduction in AMR voltage and may subsequently begin to influence PPM return rate of returns exhibiting EOS damage.

Customer and Supplier Communications

In summary, ESD design styles can lead to EOS damage if proper protection design techniques and precautions are not followed. For any choice of protection design that is implemented it is imperative that the ESD designers understand the applications of the specific pins, any potential impact on EOS, and also pay attention to any other cautionary notes.

Much of the EOS damage can be avoided by proper upfront communication. The customer must inform the designers about the application voltage range, any possible voltage overshoots and undershoots, etc. The supplier must have proper knowledge of the trigger and holding voltages of the ESD protection clamps, adequate margin between maximum operating voltage and breakdown, and choose clamps that function in this “ESD design window” safe operation region, and so on. Many more example recommendations are given in reference [1].


  1. Industry Council on ESD Target Levels, “Understanding Electrical Overstress (EOS)”, or JEDEC Publication JEP174, October 2016.

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