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IEC 61000-4-2 Emulation and Simulation

The Ideal, Real and Virtual world of ESD

ESD qualification requirements for systems rely heavily on ideal discharge models such as IEC 61000-4-2. “IEC Gun” emulation (e.g., reproduced in the lab) of the discharge into a system represents a “typical” discharge resistance of a hand-held metal object by a “typical” human who is charged to various test voltage levels. 3D field solver and nodal simulation (e.g., reproduced in a virtualized computer model) methods can also be applied to help speed the comparison of different configurations and test conditions.

HMM (human metal model) is a broadly used term for system and device models which approximate a human body with a metal object (such as tweezers) making the final contact (Figure 1) to a semiconductor device installed on a circuit board. As a byproduct of ESD “guns” (also confusingly referred to as “simulators”) developed to mimic this type of event, these discharges create substantial E- and H-fields in the RF/EMI spectrum that can couple throughout all the nearby circuitry and not just the devices in the nodal circuit model. Additionally, the wide range of calibration tolerances in the IEC definition for gun compliance leaves room for dramatic variances in current pulses currents (Figure 2) and total energy delivered into an arbitrary load or clamp (Figure 3). This of course may create equally dramatic variation in measured robustness and repeatability between guns, between labs in different locations, between testing dates at the same location and between system configurations.

Figure 1: IEC 61000-4-2/ISO10605 human metal model representation


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Figure 2: Several simulation models of IEC61000-4-2 gun “emulators”


Figure 3: Different gun model total energy delivered into 2 ohms


Other forms of very common and destructive or disruptive ideal ESD discharge models are likely in the field, such as cable discharge events (CDE) and charged board events (CBE) which can be far more destructive to semiconductors at the same charge voltages (higher current and faster rise time), and can be more prevalent in an application other than HMM/IEC. While there are tight correlations between energy related failures of components in transmission line pulser (TLP) and IEC testing (see Besse, Boselli and Smedes), there are wide differences in CDE and CBE conditions, failure modes and levels.

How Does a Designer Deal with So Much Uncertainty?!?

Fortunately, there is a beachhead of sanity carved out on this Island of Misfit ESD Toys. System-efficient ESD design (SEED) or SEED co-design (See Gossner, etal.) utilizes nodal simulation of protection devices interacting with the devices they are intended to protect in a system. This provides a virtual characterization lab where various protection schemes can be at least quantifiably compared for robustness under repeatable settings. It is also possible, through lab verification and validation, to associate these results with a minimum threshold of robustness both on the IEC 61000-4-2 table, and also in the field.

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Existing Limitations for ESD Design

First order protection circuit design analysis is often based on datasheet parameters of transient voltage suppressors (TVS) devices, such as ESD ratings (VESD, IEC61000-4-2 robustness rating, etc.), and clamping voltage (VCLAMP etc.). However, these parameters are usually tested under the one condition which they will never see in a circuit: by themselves!

Since TVS devices (here called the devices under test, or DUT) are always included in a circuit in order to divert strike energy away from a device under protection (DUP), the actual clamping voltage at the TVS leads to a voltage at the protected device (VDUP) during a strike that is not the same as what might be promised on the TVS datasheet. The current diverted by the DUT (ISHUNT) is not 100%, and the residual current into the protected device (IRESIDUAL) is also not 0% (see Figure 4).

Figure 4: Actual current reconstruction scan of residual current path after TVS clamp (DUT) and ASIC to be protected (DUP)


Second order modeling of this interaction comprehends the Kirchoff’s Current Law (KCL) current division and electrical delay between these two dynamic devices, and the current, voltage, power and energy maximum limits which can cause latent or permanent damage in either the DUT or DUP (or in even the PCB traces themselves if the pulses are sufficiently energetic). Most device IBIS or SPICE models available today provide information about “clamping devices” in device I/Os, but these elements were intended to model signal integrity issues like overshoot and ringing within 5-10% above and below VDD and VSS. ESD/EOS strikes inject levels 1000x or more than what are contemplated in IBIS or SPICE models intended solely for signal integrity simulation, and while simulators will happily (and likely inaccurately) extrapolate those models out to +/- 50Amps peak for a 4mA clamp, there is no information on when the device will fail and how it will behave on the way there and beyond.

Given meaningful device models in the ESD/EOS regime, this level of approximation provides superior estimations of the system level robustness for a given conducted or contact pulse applied to a given node for the specific devices. However, it still does not necessarily address soft errors, system upsets, secondary discharges or coupled pulses into adjacent conductors and devices.

Third order modeling attempts to virtualize the entire 3D system assembly and solve the aggressor E- and B-field interactions predicted by Maxwell’s equations. Given the exorbitant amount of accurate physical and electrical model input required, this can theoretically provide the most complete and accurate representation of an ESD/EOS strike on a system. It is also extremely difficult and time consuming to assemble a meaningful representation of the system. While elegant and expensive 3D field-solvers are commercially available and extremely powerful, given the dearth of accurate ESD-regime electrical models for devices, they can also produce prodigious amounts of “garbage-in, garbage-out.”

For most quantitative “compare and contrast” analysis, though, the second order analysis with accurate models can provide excellent results for “better or worse” analysis between competing protection solutions. But no simulation under any circumstance should be assumed to answer all questions, nor be extrapolated outside its limited sphere of valid inputs. The pass/fail criteria of a system are defined at the system level.

For example, one TVS device may clamp harder and faster than another device. This additional shunt current may inject undesirable currents and rise times into power rails or ground, causing secondary upsets on other devices. Assumptions outside the scope of any limited simulation are not necessarily valid.

Questions and Considerations for Simulation and Emulation of ESD Events

Following is a list of items to resolve before diving into ESD robustness analysis and optimization on the virtual workbench or actual test table:

  1. What are the system level ESD protection requirements? What kind of “aggressor pulse,” given ambient voltages, charge capacitance and discharge impedance, is the system likely to be subjected to in the user environment?
  2. What type of lab emulation model is appropriate to represent the “aggressor pulse” definition above? Is HMM, CDE or CBE applicable? All of them? A customized model for a particular application unique to the product environment?
  3. Do minimum regulatory requirements exist for the system? Are they sufficient to ensure acceptable return/failure criteria in the field for your product?
  4. What circuit simulation platforms are best suited? Online simulators with integrated libraries? Open Source and Free SPICE simulators? Commercial licensed platforms?
  5. Where do I get the models to simulate with? What are the model sources and data sources for those models? Are they worst case, typical or “best in class” marketing attempts to gain design wins?
  6. What circuit models are available for the DUT and the DUP? IBIS? SPICE? Are they applicable to the ESD aggressor pulse regime (10-60A peak, <1ns rise times, etc.) or are they merely intended for small-signal signal integrity modeling?
  7. Who is providing the device models? Commercial vendors on their best performance data? 3rd party measurements of actual devices?
  8. What are the failure criteria for the device models? Peak current or voltage? Total energy per pulse? Integrated power to fail? I2t fusing? Combinations?
  9. Are the parasitic elements of the simulation sufficient (or necessary) to predict the failure mode? For example, does the model create inductive spikes that replicate gate oxide breakdown voltages accurately? Do the devices have that kind of structure that needs additional elements?)
  10. How do I ask a vendor any of these questions if they have never heard of “SEED” in the first place? How do I get through the first Application Engineering layer of a semiconductor vendor and all the way to the TLP/ESD expert in a TVS or ASIC company?
  11. What “gun” model is to be used? A model characterized specifically to match the gun used in your qualification lab? A worst case model for all guns? An array of aggressors including IEC, CDE and CBE?
  12. How much simulation and emulation is enough? Is there a limit on the amount of bill of materials (BOM) costs which can be allocated to protection strategies? Does a simulation need to be done anyway to identify how much margin or risk is likely without additional protection?
  13. How can the results of the simulation be validated in the lab? Are there industry test methods available or characterization labs which can be hired? Are there baseline tests and models which can be run as a test bench for the simulator? What should an evaluation board look like for correlation testing?
  14. What about EOS that is not related to ESD? Can other pulse types (surge, lightning, electrical fast transients) be modeled with SEED? Are the ESD models necessarily applicable? Are there different failure criteria?


  1. Gossner, H., Duvvury, C., “System Level ESD Co-Design,” Wiley – IEEE, 2015.
  2. P. Besse, J. P. Laine, A. Salles, and M. Baird, Correlation between system level and TLP tests applied to standalone ESD protections and commercial products, in Proc. 32nd EOS/ESD, Oct. 2010, pp. 16.
  3. G. Boselli, A. Salman, J. Brodsky, and H. Kunz, The relevance of long-duration TLP stress on system level ESD design, in Proceedings of 32nd EOS/ESD Symposium, EOS/ESD 2010, pp. 31-40. EOS/ESD Symposium Proceedings, 2012.
  4. T. Smedes, J. van Zwol, G. de Raad, T. Brodbeck, H. Wolf , “Relations between system level ESD and VFTLP” Proceedings EOS/ESD Symposium, pp. 136-143, 2006.


Jeffrey Dunnihoo is the founder of Pragma Design in Austin, Texas; specializing in interface design architecture and ESD, EOS, and other transient analysis. He has presented at conferences sponsored by the IEEE EMC Society, the EOS/ESD Association, and ISTFA, and has recently co-authored a new textbook with other ESD experts on ESD co-design fundamentals. He has also been a contributor to industry groups and standards bodies, such as USB, IEEE 802.11, VESA/DisplayPort, and the ESD Industry Council, and has served on EOS/ESD Association, Inc. systems and testing working groups. He can be reached at

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