Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR capability of the chips.
As we move through the speed grades, the physical layer design of PCBs, cables assemblies, and connectors evolves. The latest data throughput and latency-driven signaling updates challenge previously acceptable design trade-offs. We’ll review interconnect design progression from 1Gbps transmission line data rates to the 224Gbps rates to highlight the on-going refinement of design goals.