ESD in advanced IC bonding technologies

The integrated circuit technology scaling roadmap is investing heavily on advanced bonding technologies. Bonding multiple chips together into a single system with extremely short interconnects promises to continue increasing integrated-circuits performance regardless of the transistor scaling slowing down. “Chiplets”, “2.5D bonding”, “3D bonding”, “chip-on-wafer”, “wafer-on-wafer” and “heterogeneous integration” are some of the terms associated with these advanced bonding technologies. However, system assembly during advanced bonding also raises concerns of electrostatic discharges (ESD).

This year Chiplets Solutions for Custom IC (CHISIC) Design Workshop at IEEE Custom Integrated Circuits Conference (CICC) will feature the talk “ESD in advanced IC bonding technologies” by Marko Simičić, imec which will look into ESD concerns and solutions from three points of view: ESD protection, ESD testing and ESD prevention, with focus on circuit design.