Part 1: Top-Level Description of the Design Problem

This is the first of a series of articles devoted to the design, test, and EMC emissions evaluation of 1- and 2-layer PCBs that contain AC/DC and/or DC/DC converters and employ different ground techniques. In this introductory article, we present a top-level block diagram description of the design problem under research. The subsequent articles will be devoted to the specific parts of the design, and subsequently to the RF emissions performance of the PCB assembly. This is a research in progress. The goal of this study is to evaluate the impact of different grounding strategies and the tradeoff with other design constraints that designers often face.

1. Introduction

Electronic products that are sold in the marketplace must undergo a series of Electromagnetic Compatibility (EMC) tests to demonstrate compliance to industry and regulatory requirements. One aspect of the requirements focuses on evaluating a device’s conducted and radiated emissions performance. These two aspects of EMC are important as they measure a device’s ability to produce noise that can interfere with the AC or DC mains as well as radiated noise impacting other devices in the surrounding environment. One of the biggest challenges industries face as they design and manufacture electronic devices is EMC performance related to grounding and power conversion circuitry. Most electronic devices have some type of power converter in use. Common examples are converting 240VAC or 120VAC to 24VDC or lower logic level voltages such as 5VDC, 3.3VDC or lower. Linear power converters often have thermal dissipation concerns, and as a result, class D switching converters are used to save on power dissipation and improve the overall efficiency of the converter. Class D switching power converters typically generate conducted and radiated emissions that can be measured during testing from 150kHz to as high as 300MHz or higher. The contributions come from the fundamental switching frequency, the first set of harmonics, and the broadband noise from ringing and oscillations found in and around the switching devices and magnetics. Many industries including Automotive, Consumer, Office Environments, Medical, Industrial, Commercial, and Aerospace face these challenges. Some of the EMC specifications that apply to these industries are: CISPR25, Title 47 CFR Part 15, ICES-003, IEC 60601-1-2, EN 61000-6-4, EN61326-1, CISPR11, CISPR22, DO-160, MIL-STD-461.

This article is organized as follows. Section 2 presents the top-level functional block diagram with the EMC considerations. Section 3 is devoted to the individual functional blocks. In Sections 4 and 5, several grounding schemes for 1-layer and 2-layer boards, respectively, are shown. Section 6 provides a brief outline of the next article.

2. Top-Level Schematic – Functionality and EMC

Figure 1 shows the functional blocks of the PCB assembly.

The board will be capable of accepting either an AC or DC input. The AC to DC conversion will take part in Partition A of the board (not drawn to scale). The DC to DC converter in Partition B will accept 24V DC input either from the AC/DC converter in Partition A or from an external source.

In Figure 2 we show the EMC consideration superimposed onto the functionality requirements. These considerations include both conducted and radiated emissions.

The external AC and DC inputs and I/O circuitry provide noise-coupling paths (for conducted /radiated emissions) from the converters. Additional noise paths exist between the two converters themselves, as well as between the converters and the rest of the circuitry in Partition B. 

Switching Class D power converters contain switching waveforms that produce harmonic noise and ringing that causes broadband high-frequency emissions. The implementation of EMC design controls and PCB layout will affect the EMC performance of the PCB assembly and associated cabling.

3. Functional Block Details

Figure 3 shows the block diagram of the AC/DC converter.

The converter stage employs a filtering block, full-wave rectifier, controller, and a transformer which provides isolation between the two partitions.

Figure 4 shows the block diagram of the DC/DC converter.

24V DC input to the converter comes either from the AC/DC converter or from an external linear power supply input. The control IC contains the switching transistor and the feedback signal detection.

Figure 5 shows the block diagram of the I/O circuitry.

The I/O circuitry contains a microprocessor powered by 3.3V DC as regulated by the DC/DC converter. A real-time clock is provided so that analog values from the thermocouple can be recorded in memory. An unshielded multi-conductor cable with a length of 1 meter will be connected between Partition B and a thermocouple. This cable is likely to carry some of the common-mode emissions from the converters and the microcontroller.

4. One-Layer Board Topologies

This Section describes two 1-layer PCB topologies under study, referred to as Case 1.1 and Case 1.2, respectively.

Figure 6 shows the grounding scheme for Case 1.1, where the ground is routed exclusively as traces on the top of the board.

This case represents some of the more challenging designs that are subject to significant cost and space constraints. In this scenario, the designer has very few options to apply EMC rules-of-thumb and best design practices. It is likely that this design will have challenges meeting RF emission requirements and may require additional filtering components to address non-compliances. 

Figure 7 shows the grounding scheme for Case 1.2, where ground floods are introduced on the top of the board.

Case 1.2 is similar to Case 1.1, but with fewer space constraints in its application. Here the designer has more opportunities to improve grounding and reference areas. Adding additional ground and/or reference areas improves RF return paths and can reduce RF emissions. The additional copper areas will likely help with thermal power dissipation, as well.

5. Two-Layer Board Topologies

This Section describes two 2-layer PCB topologies under study, referred to as Case 2.1 and Case 2.2, respectively.

Figure 8 shows the grounding scheme for Case 2.1, where the bottom layer is a mostly solid reference plane with some slots accounting for the need to route signals on the secondary layer.

This design moves closer to the ideal reference plane implementation on the secondary side of the PCB. It has significantly more reference copper to help reduce RF emissions, but the designer requires some use of the secondary side to route power and signal nets. These nets create cut-outs (slots) in the secondary side of the PCB and can negatively impact RF emissions. Stitching vias are used to connect some copper reference areas on top and bottom layers.

Figure 9 shows the grounding scheme for Case 2.2, where the bottom layer is a complete ground flood with via stitching to the top-layer ground areas.

This design implements a solid reference plane on the secondary side of the PCB. Stitching vias are used to connect the reference planes between the top and bottom layers. This design approach can improve RF emissions while potentially reducing the number of filtering components needed for compliance.

6. Future Work

The next article will provide the schematic details of each functional block for the baseline design. The article will also address some of the EMC design controls that can be implemented on the schematic level.