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ESDA Working Group 14, System Level ESD

Question: I have heard cable discharge event (CDE) being described as being similar to transmission line pulse (TLP). Is this a good description of the event? TLP is usually a simple coax cable, but most user interfaces have multiple conductors including shields, power lines, and twisted pair data lines. It seems that TLP might be too simple a model.

Answer: Classic cable discharge event (CDE) is the discharge that occurs when an interface cable becomes charged and then discharges when it is plugged into an electrical system. You are correct, TLP can be helpful in understanding CDE, but as you suspect CDE is much more complex than traditional TLP. In fact, it is fair to say there is no single CDE description. There are different CDE scenarios depending on cable characteristics and quality, how the cable is charged, the environment in which the event occurs and how the discharge occurs. We will first discuss CDE on an unshielded twisted pair and then show how the addition of shielding and properly designed connectors change the situation radically.

Other than coaxial cable, an unshielded twisted pair is the simplest data cable type. Most Ethernet cables are a bundle of 4 unshielded twisted pairs. The classic way for a cable to become charged is by dragging it on the floor and charge builds up on the insulator. Over time the charge may migrate to the conductors, but even if it doesn’t the cable is now at an elevated potential. Plugging the cable into a system, as shown in Figure 1, will create a CDE [1]. How much current occurs during the event depends more on the environment than it depends on the cable properties itself. The two wires in the twisted pair will likely be at essentially the same elevated potential with respect to their surroundings. The cable discharge event will be governed by the transmission line properties of the twisted pair with respect to ground potential, for example, the floor.

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Figure 1: CDE of an unshielded twisted pair

We can infer some aspects of this kind of CDE from the impedance formula for a transmission line:

The impedance depends on the inductance of the conductor and the capacitance to ground. If the cable is held well above ground, C will be small. This indicates that the characteristic impedance will be relatively high. Experiments on telephone cables have shown that the average impedance of a cable with respect to ground is approximately 150 Ohms [2]. Therefore, the current level will not be as high as expected, if you assumed a 50-ohm impedance. The current level will still be high, however, if we use 150 ohms as the characteristic impedance and charge to 1000 V the discharge current would be about 6.7 A. This is the rough current level that Ethernet ports can be subjected to and must be designed to handle. The length of the cable will determine the CDE pulse duration.

Most modern interface standards, such as USB and HDMI, use much more complex cable arrangements and several features of these cables tend to mitigate the severity of CDE considerably. For discussion, we will use USB 2.0 cable as an example, since it is much simpler than USB 3.x, HDMI or any of the other multi twisted pair cables available, but it includes all of the important features. Figure 2 shows the cross-section of a quality USB 2.0 cable [3]. Note that USB 2.0 cables come in a wide variety of qualities. In some cables the shields may be of low quality or may even be absent. In other cases, the shields are not actually connected to the connector shields at one or both ends of the cable. This leads to a large variety of potential cable discharge events.

Figure 2: Cross-section of a quality USB 2.0 cable. The left diagram illustrates the various elements of the cable, while the right diagram shows the various capacitances between conducting elements. Copper is illustrated in orange and the conductor jackets have their normal color except white is illustrated as grey.

Similar to the unshielded twisted pair, a charged insulating jacket means that the inner conductors will be at an elevated potential, even though the inner conductors may have no net charge on them. If the outer shield provides a good shield, all of the inner wires will be at the same potential as the shield due to capacitive coupling, as illustrated on the right side of Figure 2. Even with the relatively high resistances of modern cable insulators, charge will redistribute itself in the cable over the time period of minutes [3]. The potential of all inner conductors at the time of a cable discharge event will then depend on the amount of excess charge, resistivities of the different insulators and the capacitances between the conductors. In general, however, charging the outside of the cable will result in all shields and inner conductors being at an elevated potential, but the potential differences between the shields and other conductors will be relatively small.

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How the discharge occurs affects the nature of the stress to the system it is being plugged into [4]. USB connectors, as well as many other connector types, have been designed to force a specific connection sequence; outer shield first, power pins next, and finally data lines, see Figure 3. We will first discuss a quality USB 2.0 cable and then discuss issues if the quality is less than ideal.

Figure 3: Representation of a USB cable being inserted into a system. For convenience, the power and data are shown connecting to ground as resistors. Any shield specifically around the data lines has been left off for simplicity.

We will again consider a case in which the cable is charged by dragging it across the floor. As discussed above, all of the conductors on the cable will be at roughly the same high potential. As Figure 3 shows, the first contact between the cable and the system will be the connector shield, creating the CDE. The current during this event will travel through the connector shields on both the cable and the system, likely bypassing sensitive circuitry, although ground currents could cause system upset. The current levels will be similar to the currents discussed for the unshielded twisted pair discussed above.

Once the outer shield is grounded by contact, the relative voltages between the shield and inner conductors will remain the same as they were before the discharge [3]. The stress when the data lines finally contact, probably milliseconds after the shield connection, will likely be rather small. It is for this reason that classic CDE should not be a major failure risk for USB and other shielded twisted pair interfaces such as HDMI and Display port.

Cable quality can be an issue, however. Consider a cable in which the outer shield is not properly connected to the connector shell. In this case, the CDE current will be carried by the power lines. More serious still is a “special” cable designed only to carry data with no need to provide power. If the connector shield is not connected to the connector shell, or there is no connector shell, the full stress will be to the data lines.

Cables already plugged into a system can also carry ESD stress to a system as analyzed by Tim Maloney [5]. Another cable-related event that can inject significant current into a system is when a charged device, such as a mobile phone or camera, is plugged into a cable already connected to a system.

In summary, TLP ideas are helpful in understanding CDE, but it is an imperfect analogy. A full understanding requires knowledge of how the cable is charged, details of the cable design, including shielding and connector design as well as how the system begins plugged into is designed. The quality of the cable is also of great importance. A bargain cable that does not connect the cable shield to the connector shield can turn a harmless discharge to chassis ground into a direct strike to sensitive data lines. In that case, the cable was not a good bargain!

The Electrostatic Discharge Association (ESDA) System Level ESD Working Group (WG14) would love to hear about any CDE experience that you have, as the working group works on a Standard Practice test method for CDE. Send your experience to me at or to the working group chair Tom Meuse at


  1. W. Stadler, T. Brodbeck, J. Niemesheim, R. Gaertner, K. Muhonen “Characterization and Simulation of Real-World Cable Discharge Events,” 2009 31st EOS/ESD Symposium.
  2. J.J. Goedbloed, “Prediction of Common-Mode Voltages Induced in Telephone-Subscriber Lines by Broadcasting Transmitters at Frequencies < 30 MHz” Nat. Lab. Unclassified Report 008/92, Philips Electronics N.V.
  3. W. Stadler, J. Niemesheim, A. Stadler, S. Koch, H. Gossner, “Risk Assessment of Cable Discharge Events,” 2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
  4. S. Marathe, P. Wei, S. Ze, L. Guan and D. Pommerenke, “Scenarios of ESD discharges to USB connectors,” 2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Tucson, AZ, 2017, pp. 1-6.
  5. T. J. Maloney, “Primary and Induced Currents from Cable Discharges,” 2010 IEEE Electromagnetic Compatibility Symposium, 2010.

Robert Ashton is the Chief Scientist at Minotaur Labs, a provider of ESD and latch-up testing located in Mesa, Arizona. He received his BS and PhD degrees in Physics from the University of Rhode Island. After Post-Doctoral positions at Rutgers University and Ohio State University he joined AT&T Bell Laboratories in the field of integrated circuit technology development. He stayed with Bell Laboratories, and its spinoffs Lucent Technologies and Agere Systems for 23 year where he became involved with on chip ESD protection. After leaving Agere Systems he became Director of Technology of White Mountain Labs, an ESD and latch-up test house. He then spent 10 years with ON Semiconductor in their discrete products division, providing and managing application engineering support for transient voltage suppression products. He has published numerous articles on ESD testing of integrated circuits, test structure use in integrated circuits, and CMOS technology development. He has also presented tutorials on ESD, latch-up, and transmission line pulse testing at IEEE and ESDA conferences. Robert is an active member of ESDA working groups for device testing standards and the JEDEC latch-up working group. He has been a regular member of the EOS/ESD Symposium technical program committee. Robert served on the ESDA board of directors from 2011 to 2013 and was business unit manager for advanced topics in 2012 and 2013. He is currently serving as vice chair of the human metal model (HMM) and System Level ESD Modeling working groups.

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