What makes a good ESD model?
A good ESD model should offer the following features:
- Coverage of all device effects relevant to the ESD simulation task
- Accuracy within the desired range of operation (voltage, temperature)
- Simplicity – fast execution
- Continuity – good convergence
Let’s look at some examples of potential model deficiencies. Static ESD models lack coverage of transient effects as mentioned earlier. This can be problematic, as demonstrated by the following HBM (human body model) simulation study. An HBM current pulse has a rise time of about 10ns followed by an exponential tail. Traditionally, HBM device damage levels have shown good correlation with 100ns TLP data, although the two stress waveforms are completely different. Extracting a static ESD model from the same 100ns TLP data may be convenient. However, such a model may give an unrealistically high stress voltage at the peak of the HBM pulse. This is because the device may be subject to self-heating, visible in the I-V curve as an over-proportional rise in voltage also known as I-V roll-off. At the HBM peak, around 10ns, the self-heating is still relatively low, and the static 100ns model would give an inflated voltage. This issue may be relevant for the protection of devices with voltage-dependent breakdown, e.g. gate oxides of MOSFETs. A static 10ns model may therefore be better for simulating the HBM peak voltage.
Figure 1 demonstrates this with simulation results of a simple ESD diode under 2kV HBM stress. Two different static models obtained from curve fitting to 10ns and 100ns TLP curves (Figure 2 on page 18) were used. A transient diode model with self-heating effect [1] was also evaluated for comparison. This would be a better choice if accurate results over the entire time range were paramount. During a very fast ESD stress event like a charged device model (CDM), a transient model would furthermore be able to predict voltage overshoot caused by the turn-on delay of an ESD device [2].
One example of insufficient accuracy of an ESD model is illustrated by looking at a “snapback” model of an NMOSFET describing the turn-on of its parasitic lateral BJT. TLP measurements are often available for the grounded-gate case, which gives the highest turn-on voltage (Vt1) and therefore the strongest snapback effect. However, with an applied Gate bias the Vt1 would be significantly reduced, as shown in Figure 3. There may also be an impact on the “on” voltage during BJT mode and on the failure current level. A simple ESD model would not take these effects into account, which would be important for simulating actively triggered NMOS rail clamps that can operate in BJT mode, for example.
Models with discontinuities in their behavior may have poor convergence. This may significantly increase the simulation time or even prevent the simulation from completing altogether. An example would be a MOSFET snapback model with abrupt transition between the “off” and “on” states of its parasitic BJT using a simple “if” statement in the model code. Even a discontinuity in the first derivative of a model may cause poor convergence. Abrupt state transitions can be avoided by using transient relaxation techniques in the model code, which may also be used to capture the effects of turn-on or turn-off delay. An example of a resistance R(t) transitioning between two values using a simple exponential relaxation function s(t) is shown in the following equation.
R1 and R2 are the resistance values before and after the transition, respectively, t0 is the time when the transition begins, and τ is the time constant of the transition.
How are ESD models enabled?
Due to the very specific purpose that ESD models serve, there are several ways of enablement. A designer typically works in a CAD environment where circuits are drawn as schematics that can be used for simulations. The symbols used in schematics are taken from a standard PDK device library.
Ideally, a device symbol used for regular “functional” simulations of a circuit would be the same as for ESD simulations. Obviously, this would only be feasible if the ESD model featured the same number and types of device terminals. In this case a universal device model could capture both operating regimes. However, due to their narrow focus, ESD models are often not suitable for functional simulations that require accuracy of device leakage and parasitic capacitance, and standard device models may not be used for ESD. Furthermore, ESD models typically only work well at room temperature and assuming typical process conditions. For these reasons, universal models may be difficult to develop.
Alternatively, a switch could determine whether the standard device model or the ESD model should be used. This may be a global user variable in the simulation suite or a variable specific to a device symbol. A model switch example using a wrapper or “shell” model approach is shown in Figure 4 for a two-terminal device. The ESD model is enabled via two ESD extensions, one put in parallel with the standard model and another one added in series with it.
Using dedicated device symbols for ESD simulations is an alternative enabling method. In this case, the designer would have to create separate ESD schematics with these symbols for ESD simulations. Such ESD symbols could be part of a special ESD library that gets distributed with the PDK. If a designer only had an ESD model deck, they would need to take care of completing the CAD enablement themselves. This may include tasks like creating a new device symbol, a list of device parameters, and netlist instructions specific to the simulator that is used. Without CAD enablement, ESD simulations may only be performed from bare circuit netlists, without any schematic support.
References
- M. Stockinger, J. Miller, “Characterization and Modeling of Three CMOS Diode Structures in the CDM to HBM Timeframe,” Proc. EOS/ESD Symposium, 2006.
- M. Stockinger et al, “CDM Protection Design for CMOS Applications Using RC-Triggered Rail Clamps,” Proc. EOS/ESD Symposium, 2009.
