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ESD Device Modeling: Part 1

Why are ESD device models needed and what are they used for?

SPICE simulations for predicting the behavior and performance of circuits under ESD stress have become indispensable in semiconductor design. This has driven the development of ESD device models. A high level of predictive capability is needed to ensure first-pass ESD success of a new product and to avoid costly design re-spins. Accurate modeling of protection circuits also enables the initial protection design development with optimization and verification for the different ESD stress tests of HBM and CDM.

ESD models may be used for simulating on-chip integrated circuits or system (board) level circuits with discrete electronic components like diodes, TVS devices, and bipolar junction transistors (BJTs). While on-chip simulations have received more attention in the past, the system-efficient ESD design (SEED) methodology [1] has increased the need for component ESD models, and there is, in principle, not much difference between the two types.

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The standard device models that circuit designers typically find in a process design kit (PDK) cover the normal operating voltage and current ranges. During ESD, normal operating conditions are exceeded, and the standard PDK models either become inaccurate or stop working altogether, which may result in convergence issues or crashed simulation runs.

Furthermore, certain devices may start operating in entirely different conduction modes during ESD. The higher voltage and current levels can activate so‑called “parasitic” devices. They are usually “dormant” during normal circuit operation and can, therefore, be ignored by standard PDK models. Examples of parasitic ESD devices are given below.

The first example (Figure 1) is a diode structure built in a CMOS technology. A P+ region (Anode) inside an N-well (Cathode) forms the main junction. The corresponding PDK symbol is a two-terminal device, and its standard model resembles the well-known diode I-V characteristic. However, this neglects the fact that this diode actually forms a three-terminal device –
a BJT with Emitter (Anode), Base (Cathode) and Collector (P-substrate).

Figure 1: Cross-section and equivalent symbols of a P+ in N-well ESD diode with shallow trench isolation. The parasitic well diode is also shown. For functional simulations, two simple diode models are sufficient. For ESD, the main diode becomes forward biased and a parasitic BJT model should be used.


During normal operation, diodes are usually reverse biased, and the model must accurately capture diode leakage and capacitance. During ESD, diodes may become forward biased, and therefore the parasitic BJT gets activated and produces significant Collector current. Neglecting this effect may lead to wrong ESD simulation results. This is illustrated in Figure 2 using an example ESD protection design with two IO pads and assuming an ESD zap from IO1 to IO2. Diode Dp conducts most of the ESD current from IO1 to the VDD rail, but some current gets shunted directly to VSS via the parasitic PNP. Diode Dn conducts most of the current from the VSS rail to IO2, but it collects some current directly from VDD via the parasitic NPN. The rail clamp shunts current from VDD to VSS, but this current is reduced by both Collector currents of the BJTs. Using diode models without BJT effect would result in an oversized rail clamp potentially wasting chip area.

Figure 2: ESD discharge path between two IO pads illustrating the effect of parasitic paths due to the BJTs. Only ESD devices participating in the discharge path are shown.


The second example of a parasitic ESD device is an NMOS transistor (Figure 3). Its PDK symbol typically has four terminals – Drain, Source, Gate, and Body – and focuses on MOSFET channel conduction, junction leakage, and various capacitances between the four terminals. During ESD, a parasitic lateral BJT with Emitter (Source), Base (Body) and Collector (Drain) can form a strong current path under the channel region. This mode is often referred to as “snapback” of the MOSFET if the BJT conduction is self-sustained by avalanche breakdown at the Drain junction. ESD devices often leverage this BJT mode to achieve high-current conduction capability with small on-resistance.

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Figure 3: Cross-section and equivalent symbols of an NMOS transistor. During ESD, a parasitic BJT model with avalanche breakdown effect needs to be included in parallel with the NMOS model to capture the snapback behavior.


The third example (Figure 4) is a silicon-controlled rectifier (SCR) formed as a parasitic device between a P+ in N-well junction, e.g. the Source-Body diode of a PMOSFET, that is in close proximity to an N+ in P-substrate junction, e.g. the Source-Body diode of an NMOSFET. If this SCR gets triggered, a strong current path is formed between the P+ region (Anode) and the N+ region (Cathode.) This may often lead to an unwanted effect called “latch-up,” but can also be leveraged for ESD clamps.

Figure 4: Cross-section and equivalent symbols of an SCR formed between two diode structures. The SCR is formed by the cross-coupled parasitic BJTs of the diodes and needs to be modeled for ESD.


What measurement data drives ESD model development?

Transmission line pulse (TLP) testing is considered the workhorse for all types of ESD characterization [2], and ESD models are usually matched to TLP data. A TLP test applies rectangular-shaped stress pulses via a transmission line (e.g. a 50 Ohm coaxial cable) to a device under test (DUT). The pulse length of a “standard” TLP system is typically 100ns. If the pulses are shorter than 5ns, the system is called a “very fast” TLP (VF-TLP) system. The voltage and current waveforms at the DUT get measured, and a discrete I-V pair gets extracted by averaging the waveforms over a time window (e.g. 70%-90% of the pulse), as shown in Figure 5. After the stress pulse, the DUT is assessed for potential damage by a leakage measurement. By incrementally stepping up the level of the stress pulse to the damage level of the DUT, a full I-V curve is obtained. It is important to note that using different TLP pulse lengths may result in different I-V curves due to time-dependent effects in the DUT, e.g. transient voltage overshoot or self-heating.

Figure 5: Example of a 100ns TLP voltage waveform with measurement window.


For most ESD model development tasks, TLP measurements are performed on silicon wafers rather than packaged parts due to the needed accuracy. For VF-TLP characterization, the use of RF wafer probes is of great advantage. This may require the use of dedicated probe pad frames containing the ESD devices.

TLP measurements are typically performed at room temperature, which is the focus point of ESD events and usually capture only a small statistical sample. This is due to the fact that manual DUT and probe placement are common. However, fully automated TLP systems exist enabling a statistical approach to TLP characterization. This may also be an advantage to ESD device modeling, e.g. for capturing the effects of process variations. However, it is quite usual to limit ESD models to typical process conditions without covering process corners.


What ESD models exist today?

A variety of ESD models have been published by academia and by semiconductor companies. In advanced technology nodes, semiconductor fabs have taken on the task of including ESD models in their extended PDKs, but this has not always been the case. Today’s ESD model landscape is vast, and providing comprehensive references would exceed the scope of this article. These individual ESD models are usually created for very particular simulation tasks. Universal coverage of all device behaviors or usage modes is typically not an imperative.

ESD models created by the industry have been known for “getting the job done,” with the least amount of modeling effort and sometimes with a complete disregard of the underlying device physics. This has led to “empirical” or “curve fitting” models whose accuracy has in many cases been excellent. Academic models, on the other hand, have been focusing more on device physics. This has resulted in quite impressive, but complex model formulas and has enhanced scalability to process parameters and device geometry. However, in some cases, academia has “tied their own hands” by an unwavering effort to use fully physical models, even for the most complex device effects, which may be more easily captured by empirical (behavioral) modeling. One example is the physical modeling of Band-to-Band tunneling effects for capturing the snapback effect of MOSFETs in advanced sub-micron technologies.

As of today, there are no standard ESD device models available like e.g. the BSIM model for MOSFETs. The Compact Modeling Coalition (CMC) of the Silicon integrated Initiative (Si2) has started an effort to drive standardization of ESD models. It is expected that this will decrease the time and effort required to design and analyze ESD protection circuits.


How can ESD models be categorized?

There are different ways to categorize ESD device models. One way is to look at the type of device, for example. The following five categories may cover the most important types.

  1. BJT model for “ESD diodes” in forward conduction (3 terminals: Emitter, Base, Collector)
  2. BJT “snapback” model for MOSFETs (4 terminals: Emitter, Base, Collector, Gate)
  3. SCR model (2 or more terminals: Anode, Cathode, optional control terminals)
  4. Breakdown model for Gate oxides and diodes in reverse conduction (2 terminals)
  5. Resistor model (metal, poly or diffusion) with self-heating (2 terminals)

Another way to categorize ESD models is to look at the beforementioned empirical vs. physical model distinction. However, hybrid implementations may also exist.

New ESD models are usually coded in Verilog-A due to its versatility and ease of use. Most SPICE simulation suites provide a Verilog-A interface to enable custom models. Some ESD models, however, don’t even need any new code. Such sub-circuit models simply use devices from the standard PDK in a clever way, for example, MOSFETs, diodes, controlled voltage or current sources, capacitors, inductors, or switches. This would be another way to distinguish types of ESD models.

Although an ESD event is fundamentally transient in nature, the simplest ESD models are quasi-static “DC” models without any built-in time dependence. Such models try to fit models to I-V data, often obtained with only a single TLP pulse length. The distinction between DC and transient ESD models is another way of categorization.


References

  1. Industry Council on ESD Target Levels, “White paper 3 – System-level ESD,” Part I and Part II, https://www.esdindustrycouncil.org/ic/en/documents.
  2. T. Smedes, “Transmission line Pulse Testing: The Indispensable Tool for ESD Characterization of Devices, Circuits and Systems,” In Compliance, August 2017.


Michael “Michi” Stockinger
received his Ph.D. in electrical engineering with highest honors from Vienna University, Austria, in 2000. His doctoral research focused on the optimization of ultra-low-power CMOS transistors. In 2000, he joined Motorola’s Semiconductor Products Sector in Austin, Texas, changing to Freescale Semiconductor in 2004 and to NXP Semiconductors in 2016. Michael’s focus has been on ESD protection and LU prevention for advanced CMOS products. He is Technical Director of ESD design in NXP’s Microcontroller division. Michael’s on-chip ESD solutions have been implemented in the Kinetis, i.MX, and ColdFire product lines. His latest research interests are in the field of on-chip protection solutions for system-level (IEC) transient immunity. Michael was awarded the 2001 EOS/ESD Symposium Best Paper award, the 2003 EOS/ESD Symposium Best Paper and Best Presentation awards, and the 2013 EOS/ESD Symposium Best Paper and Outstanding Paper awards. He has authored over 35 technical papers and holds 25 patents. He has served in the TPC of several EOS/ESD Symposia, International Reliability and Physics Symposia, and International ESD Workshops and teaches an ESDA tutorial.

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