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ESD Designers’ Headache with Multiple Automotive Test Requirements, Part I

A Review of ESD-EMC Co-Design Challenges

The trend toward society’s “smart‑electrification” is driving the need for ESD immunity at the system-level. IEC 61000‑4‑2 [1] defines how to perform the electrostatic discharge immunity test at the system level. Until about 15 years ago, protecting against such events involved implementing ad-hoc ESD protections (TVS – transient voltage suppressors) at board/system-level in proximity to the connectors interfacing with the “external world.” 

However, a new trend of implementing system-level robustness at the component level (i.e., on-chip) is quickly becoming standard practice, mainly stemming from the desire to reduce system/board design costs. 

While this may sound like a logical step on paper, it poses enormous challenges to the component ESD designer in that:

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Voltage Standing Wave Ratio results from an impedance mismatch between a source (an amplifier) and a load (test application). This mismatch can influence the performance of the source.
  • IEC 61000-4-2 is not applicable at the component level, so every company is struggling to understand/design proprietary characterization methods at the component level to extrapolate performance at system-level; and
  • ESD designers are now responsible for the performance of systems that they neither build nor, in many cases, know anything about.

In the automotive world, the situation is even more challenging. In addition to ESD immunity at the system level (ISO 10605 [2], adapted from IEC 61000-4-2), there is a plethora of other requirements addressing immunity to both electrical disturbances (ISO 7637 [3, 4, 5]) and to RF disturbances (IEC 62132 [6]) that must be met.

This article is divided into two parts. This first part addresses the ESD design challenges stemming from ISO 10605 specs, while the second part will review the trade-offs between ESD design and EMC immunity requirements.

Automotive System-Level (ISO 10605) ESD Design Challenges

To address the demand for area-competitive on‑chip IEC ESD Solutions (with targets in excess of 30A for Level-4 spec), the implementation of an SCR-based protection scheme is a must. Thanks to its low holding voltage, this solution is extremely advantageous in terms of power dissipation. However, this may come at a cost of a large swing between triggering voltage and holding voltage, which may cause non-uniform current conduction and render the solution ineffective. This will play a role in the specific differences between IEC 61000-4-2 and ISO 10605 from an ESD design perspective.

Different R&C Modules to Be Tested

ISO 10605 specifies four different RC combinations (R=330Ω, R=1.5KΩ, C=150pF, and 330pF), leading to pulse decay times ranging from 60ns to 600ns. The actual RC combination(s) required at the board/system level may not be known at the time of component design. The straightforward consequence is that the ESD designer needs to validate the ESD solution on all four stress waveforms, with completely different pulse widths, energy contents, and rise times. 

In [7], it was reported that an HV SCR meeting IEC Level 4 requirements (corresponding to ISO with R = 330Ω, and C = 150pF) miserably failed all other ISO stress permutations with larger capacitance and resistors. The root cause was identified in the lack of power scalability of the HV SCR caused by a static filament formation for pulses in excess of 100ns. A first-order correlation between TLP stress duration and ISO level was also established (see Figure 1 [7]). 

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Figure 1: Long-pulse TLP can mimic the impact of the various combinations of the ISO test [7]

To meet the performance target, a new architecture had to be devised with the obvious delay in product development efforts. A similar issue (i.e., lack of correlation between TLP and ISO test with R=1.5K Ω) was also reported in [8]. 

Rise-Time Sensitivity

While the four stress waveforms in ISO 10605 are fairly well defined, there is no guarantee that the same waveforms are actually exercised at the component level. This is the main conceptual issue behind the notion of implementing system-level ESD robustness at the component level, that is, the actual waveforms seen at the externally connected pins of the component are a function of the board/system-specific implementation (connecting traces and/or discrete components). In particular, inductive loads (i.e., long board traces, presence of common mode chokes, or discharges through long cables) will cause significant departure from the expected ISO 10605 waveforms, both in duration (can become much longer) and shape (oscillatory, instead of exponentially decaying). 

Unfortunately, the behavior of ESD clamps components used for system-level robustness is a strong function of the stress waveform. The bottom line is that it is virtually impossible to guarantee ESD system-level robustness at a component level without knowing all the details of the system/board
implementation. A consequence of this fact is that the practice of specifying system‑level ESD robustness on a component’s datasheet is useless and could be misleading.

A typical parameter impacted by system implementation is rise time seen at the component level. It was reported in [9] that large inductive loads on CAN pins could increase the rise time of an ISO 10650 stress to >50ns. These slow values impacted the triggering mechanism of the ESD cell, causing non-uniform triggering, hence failing to meet the specifications. Again, a novel layout with internal back‑ballasting was devised to minimize the reliance of the ESD cell on rise time. 

Common Mode Choke

Common mode chokes (CMCs) are often required to meet EMC emission requirements in differential communication busses (LIN, CAN, etc.), with a typical inductance of 100 µH. A CMC is placed directly in the ESD discharge path and, in principle, one would expect a beneficial high-frequency damping of the ESD energy. Unfortunately, a CMC displays a strong saturation behavior (due to the ferrite saturation), which results in a drastic reduction of the inductance over a certain threshold current. In addition, a CMC typically features an undesirable snapback characteristic for ESD current densities. This highly non-linear behavior can force the component-level ESD protection in and out of snapback multiple times, depending on the current density. This could lead to a non-uniform turn-on (Figure 2), causing premature failure of the component-level ESD protection [10].

Figure 2: Current density and lattice temperature of an SCR subjected to a double triggering pulse, caused the CMC presence. It can be seen that the second pulse will cause filamentary conduction in the device, which is not able to meet the ISO specification target [10]

Trade-Offs Between ESD Design and EMC Immunity Requirements

The automotive environment is extremely harsh for electronic systems. To guarantee reliable operation in all possible conditions, strict EMC immunity requirements are enforced. From an ESD perspective, EMC immunity requirements sometimes conflict with ESD requirements, making ESD-IP co-design extremely challenging. 

Immunity to Electrical Disturbances

As previously mentioned, ISO 7637 is used to characterize automotive systems against a variety of transient electrical disturbances that may occur in an automotive environment. These are caused by the various scenarios through which inductive loads (like the motor) or the battery can be switched/disconnected. The most common test pulses are 1, 2a/2b, 3a/3b, 4, and 5a/b, which differ in terms of polarities, amplitudes, pulse width, and rise time. While all different, these test pulses feature an energy content far superior to that a component level rated (HBM, CDM) ESD cell can withstand [11]. 

However, component-level ESD cells designed to meet system-level ESD immunity can withstand a much higher energy level. Hence, it is becoming standard practice to have component-level ESD cells perform dual duty, i.e., to guarantee both ESD and EMC immunity to electrical disturbances. Hence, more and more component datasheets report robustness against ISO 7637 of pins that will connect to the external world. 

The co-design of ESD immunity and immunity to electrical disturbances is not trivial. Besides the ability to withstand DC-like durations with test pulses 1, 2, and 5, slow rise times associated with them will require the ESD protection to be level-triggered. This implies the availability of a junction with appropriate breakdowns to support both ESD and EMC requirements.

Immunity to RF Disturbances

In addition to immunity to electrical disturbances, automotive systems must be robust in their defense against RF disturbances as well per IEC62132-4. A direct power injection (DPI) method is used to measure the electromagnetic immunity of an IC from 150KHz to 1GHz. The interaction between ESD immunity and DPI is not straightforward, as both ESD and DPI have fast-rising voltage edges, although with different amplitudes. 

In [11], the case of a LIN pin passing ESD immunity but failing the DPI test was reported. It was found that the noise injected into the substrate (and then coupled to the LIN pin) by the RC-triggered ESD cell during the DPI test was the culprit for the test failure. A new, level-triggered ESD cell had to be devised to address the issue. In a similar fashion, in [12], a robust RC-triggered ESD cell failed DPI testing, mainly at low frequencies. A redesign of the RC-triggering circuit was needed to address the issue, as it was not possible to design an effective level-trigger ESD cell for ESD immunity. 

From the above examples, it would seem that level-triggered ESD cells are necessary to meet DPI requirements. However, there are situations where RC-triggered ESD cells are highly desirable. One such scenario is when inductive fly-back protection is needed. This is typically the case for output pins driving inductive loads, such as external cables and/or chokes. When the power supply is switched off, it is convenient (i.e., no additional inductive flyback protection is needed) to release the energy stored in the inductors through the ESD cell. This is typically done through RC-triggering the ESD cell in MOS conduction mode to keep voltages at safe levels. As seen from the above example, functional requirements can lead to opposite design requirements on ESD cells.


The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer. Implications of EMC-ESD immunity co-design were reviewed here, along with several case studies. In Part 2 of this article, we’ll review the trade-offs between ESD design and EMC immunity requirements. 


  1. ISO 10605 “Road vehicles – Test methods for electrical disturbances from ESD.”
  2. IEC 61000- 4-2: “Electromagnetic compatibility (EMC), Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test.”
  3. ISO 7637-1:2002 (E) “Road vehicles – Electrical disturbances from conduction and coupling – Part 1: Definitions and general considerations,” Second edition 2002-03-15,
  4. ISO 7637-2:2004 (E) “Road vehicles -Electrical disturbances from conduction and coupling – Part 2: Electrical transient conduction along supply lines only,” Second edition 2004-06-15,
  5. ISO 7637-3:1995 (E) “Road vehicles – Electrical disturbance by conduction and coupling – Part 3: Vehicles with nominal 12 V, 24 V or 42 V supply voltage – Electrical transient transmission by capacitive and inductive coupling via lines other than supply lines,” 2007.
  6. IEC 62132-4, 2007, “Electromagnetic Compatibility (EMC), Integrated Circuits, Measurement of Electromagnetic Immunity 150 kHz to 1 GHz – Part 4: Direct RF Power Injection Method.”
  7. G. Boselli, A. Salman, J. Brodsky, and H. Kunz, “The relevance of long-duration TLP stress on system level ESD design,” Proceedings of 2010 EOS/ESD Symposium.
  8. P. Besse, J.-P. Laine, A. Salles, and M. Baird, “Correlation between System Level and TLP Tests Applied to Stand-alone ESD Protections and Commercial Products,” Proceedings of 2010 EOS/ESD Symposium.
  9. A. Salman, F. Farbiz, A. Concannon, H. Edwards, and G. Boselli, “Mutual Ballasting: A Novel Technique for improved Inductive System Level IEC ESD stress performance for Automotive Applications”, Proceedings of 2013 EOS/ESD Symposium.
  10. K. Nagothu, J. Di Sarro, R. Sankaralingam, G. Boselli, and M. Shrivastava, “Insights into the System-Level IEC ESD Failure in High Voltage DenMOS-SCR for Automotive Applications,” Proceedings of 2020 EOS/ESD Symposium.
  11. B. Deutschmann, F. Magrini, and Y. Cao, “Robustness of ESD Protection Structures against Automotive Transient Disturbances,” Proceedings of 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility.
  12. K. Abouda, P. Besse, and E. Rolland, “Impact of ESD Strategy on EMC performances,” in Proceedings of 2011 Workshop on Electromagnetic Compatibility of Integrated Circuits.
  13. Y. Xiu, F. Farbiz, A. Salman, Y. Zu, M. Dissegna, G. Boselli, and E. Rosenbaum, “Case Study of DPI Robustness of a MOS-SCR Structure for Automotive Applications,” Proceedings of 2016 EOS/ESD Symposium.

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