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ESD Designers’ Headache with Multiple Automotive Test Requirements, Part 2

A Review of ESD-EMC Co-Design Challenges

In Part 1 of this article (see In Compliance Magazine, May 2023), we showed that the trend of progressively migrating both ESD and EMC immunity from the system/board level to the component level is creating unprecedented challenges for the component ESD designer. We reviewed the implications of EMC-ESD Immunity co-design, along with several case studies.

With the unavoidable re-purposing of the system-level standards to validate component-level robustness (IEC 61000-4-2 [1], ISO 10605 [2]), several gaps at the standards level place ESD engineers in the awkward position of creating their own standards. Even worse, the practice of reporting system-level performance in components datasheets is completely dependent on each ESD engineer’s interpretation of the standards, hence making those specs of questionable value.

Part 2 of this article focuses on the specific ESD design challenges stemming from the fact that all relevant system-level standards were created to validate systems and not components.

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VSWR and its Effects on Power Amplifiers

Voltage Standing Wave Ratio results from an impedance mismatch between a source (an amplifier) and a load (test application). This mismatch can influence the performance of the source.

To rigorously assess the impact of the setup differences detailed in the previously mentioned standards, we offer the circuit analog shown in Figure 1. Each major component of the testing setup is included as a circuit element and the impact of those elements allowed variation to the entire circuit performance that can then be assessed. The specific components of the analog are the ESD generator (or, colloquially, ESD gun), the impedance coupling between the ESD gun and the target/DUT, the target/DUT, and the ground return path between the ESD gun and the target/DUT.

Figure 1: Circuit analogue of calibration and actual testing setups


The calibration current waveform presented in IEC 61000-4-2 [1] has become the de facto specification for system-level ESD (Figure 2). It defines a peak current, rise-time, and current values at 30 ns and 60 ns. However, as we will show, it is dangerous to use this as a design specification. Specifically, much work has been done showing large variations between ESD guns which are allowed under the the standard. Even with the same gun, the actual test setup drives significant variations. Some of the reasons/practical implementations are:

  • Calibration method/set-up does not allow a “hand-held” gun; the gun must be mounted (“tripod or equivalent non-metal low loss support” [1]). Unfortunately, the gun is made to be “hand-held” and it is commonly used in this way.
  • There are numerous reports of operator dependent variations, which are not included in the standard, and impact the calibration waveform [3]. We have experienced first-hand not only significant IEC level differences between guns from different manufacturers, but also from different gun models from the same manufacturer.
  • In general, the impact of gun positioning and operator to gun coupling cannot be ignored.
Figure 2: IEC 61000-4-2 calibration current waveform [1]

Series Elements

While system level standards do provide expected current waveforms (and a calibration method to verify them), the test-setup for which these waveforms are produced varies significantly from the test-setup in which actual device testing is performed. As highlighted in Figure 3, the calibration setup consists of a vertical ground plane which contains a specially designed target/load. The ESD gun is mounted on mechanical holder, and the ground return (or tether) is pulled into a specific shape. When devices are tested, the special target is replaced by the actual device, placed over a horizontal ground plane, with a much more arbitrary ground connection than the vertical plane presents to the target.

Figure 3: Comparison of the calibration setup and a typical actual testing setup

The ESD gun can now be held by a human operator and the position and shape of the tether is much less stringently controlled. One should not assume that the current waveform introduced to a device under test (DUT) is exactly the same as the waveform produced in the calibration setup. In fact, significant deviations in the current waveform can result, leading to unexpected performance (both pass and fail) and unrepeatable results.

While the coupling between the ESD gun and the target/DUT (Zseries in Figure 1) may seem like an insignificant contributor to the overall performance of the circuit, remember that an ESD gun in direct contact with the target/DUT is not the only configuration—in fact, the coupling between the ESD gun and the target/DUT can be quite different for some configurations. Many automotive system-level test standards [4‑7] apply discharge through a variety of gun-target couplings. In addition to the most common gun-target coupling (i.e., contact discharge), there are four other couplings (some used in conjunction), namely:

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  • Spark: air discharge
  • Wiring harness/cable
  • Common-mode choke
  • Series resistor

Spark: Air Discharge

Air-discharge is already known to produce a large variation of current waveforms—with no single waveform being deemed as “correct.” This is acknowledged in the two primary general system-level ESD Standards [1, 2]. The IEC standard describes it as:

The spark is a very complicated physical phenomenon. It has been shown that with a moving spark gap the resulting rise time (or rising slope) of the discharge current can vary from less than 1 ns and more than 20 ns” [1].

The ISO standard states it as:

The air discharge method virtually replicates ESD, as it would occur in the actual environment. In effect, this means that the impulse current waveforms delivered to the DUT are allowed (and expected) to vary significantly from pulse to pulse.” [2].

The strong relationship between the length of the air-discharge spark and the severity of the resulting current waveform means that variations in spark length translate directly into variations in current waveform. There are known factors which lead to variation in spark formation, with humidity and speed-of-approach being commonly recognized causes. However, other factors also play a role, including the shape of the electrodes between which the spark forms, and, while the standards do closely control the shape of the electrode on the ESD gun, there is no control on the shape of the target electrode.

This becomes an extremely important factor in J2962-x automotive standards [4, 5], in which air-discharges are applied directly to the BUS signal wires in the wiring harness. But current waveforms are not generally monitored in-situ during system-level testing; the person applying the discharge has no reasonable gauge of the severity of the current pulse that was actually delivered.

The current waveform shown in the IEC 61000-4-2 standard consists of a fast-rise time to a peak current, followed by a drop in current and a slower rise-time to a second peak. Figure 4 shows an expectation of two clearly distinguishable peaks (for a negative discharge) in the lower left corner. This expected waveform has a green region (indicating the 1st peak region) and a blue region (indicating the 2nd peak region). To the right of Figure 4, actual measured current waveforms are shown. These waveforms were all generated in the same test setup, by the same operator, at the same voltage level. The only variances were the speed and angle at which the operator approached the target with the ESD gun.

Figure 4: Possible expected waveform shape and actual waveform shapes from testing

More troubling is that a single waveform in this set actually damaged the DUT, while others did not. If the exact speed and angle was not reproduced by the operator, then damaged DUT did not occur, leading to a high-level of unrepeatability in testing results. Because there is no accepted air-discharge current waveform shape, it is unclear what should be expected during design and, further, what should be allowed during testing.

Another factor in air-discharge testing is the challenge of holding the pre-charge voltage on the ESD gun before spark formation. In cases where the target is a very sharp geometry (such as a wire) it is quite possible to lose charge through corona discharge. While the ESD gun may have been programmed to deliver a 10-kV discharge, at the time of spark formation perhaps only a 5-kV equivalent charge remains. In fact, doubling the discharge voltage in this case may lead to no increase in discharge current whatsoever.

So what does it mean to apply a 10-kV air-discharge to a DUT and observe no failure? Is the DUT robust or was a “soft” current waveform delivered? If a DUT fails 10-kV, does this mean it will be weak in a different test environment (or in the actual application)? Given the lack of fidelity between the programmed discharge voltage and the actual current-waveform delivered, no meaningful conclusions can be reached about the robustness of a DUT by a simple statement that the DUT passed or failed discharge voltage-level testing.

Wiring Harness/Cable

Having established the consequences of discharging through a series spark, other series elements should also be evaluated. For example, requirements to apply the discharge through a series wire or cable are not uncommon. Just as with the spark in air-discharge, the impedance of a wire or cable is not trivial, especially when considered across the large frequency spectrum of the ESD pulse. In fact, these configurations must be evaluated as transmission-line, which is not matched on either the stimulus or the load side. Reflects should be expected, resulting in deviations from a direct contact waveform.

Figure 5 shows an example of an ESD discharge applied through 5 meters of RG-58 cable, relative to the expected waveform without a cable present. If the significant reflections demonstrated in Figure 5 are not anticipated during the DUT design phase, unexpected failures can result.

Figure 5: Example of an ESD discharge through a cable

Common Mode Choke

Common mode chokes (CMCs) are often required to meet EMC emission requirements (more on that in the next paragraph) in differential communication busses (LIN, CAN, …), with a typical inductance of 100 µH. The CMC is placed directly in the ESD discharge path and, in principle, one would expect a beneficial high-frequency damping of the ESD energy.

Unfortunately, a CMC can display a strong saturation behavior (due to the ferrite saturation [10-12]), which results in a drastic reduction of the inductance over a certain threshold current. In addition, a CMC features an undesirable snapback characteristic for ESD current densities. This highly non-linear behavior can force the component-level ESD protection in and out of snapback multiple times, depending on the current density. Figure 6 shows the typical non-linear waveform of a CMC in response to a full IEC event.

Figure 6: CMC response to a full IEC event

The choke allows initial current flow, due to displacement current of the quasi-differential signal. This is followed by a “blocking” period, corresponding to the common mode signal. Eventually, the choke saturates, causing low impedance, and therefore high current flow.

This complex waveform depends on several parameters, including:

  • Discharge level;
  • Board parasitics; and
  • Unspecified/uncharacterized choke parameters (i.e., two nominally identical CMCs will yield completely different IEC results).

Series Resistors

Some automotive system-level ESD standards require testing through series resistance. When using large resistance values, the expectation is to limit the current (Figure 7). Unfortunately, there is nothing to limit voltage build-up on discharge side of resistor. Therefore, spark-over of the resistor is likely, thereby causing a full discharge into DUT (effectively emulating an air-discharge test.)

Figure 7: spark-over mechanism of contact discharge through a series resistor

Return Path

The testing setup strongly influences the ground return path. With reference to Figure 8, the common setup for IEC61000-4-2 features:

  • Board to horizontal coupling plane (HCP) capacitance inserted in the high-frequency path, and
  • Added wire impedance in the low-frequency path.
Figure 8: Common IEC 61000-4-2 implementation

The common setup for IEC62228 [8] features:

  • Metal fixture between board and HCP, tether directly to grounded HCP, and
  • Strong low-impedance bond between board and HCP.

If we look at the two return paths separately, the high-frequency return path is primarily a capacitive coupling, from the gun to the coupling plane. Coupling between board/plane adds series impedance, which can cause significant degradation of 1st peak (Figure 9).

Figure 9: First peak modulation caused by different material and thickness of the dielectric between board and HCP

If we look at the low frequency return path, it is mainly driven by the gun tether. Inserting a wire between the board and the ground reference plane adds impedance in the low frequency return path (Figure 10).

Figure 10: Effect of inserting a wire between the board and ground reference plane adds impedance in low frequency return path

As shown, the test-setup with respect to the ground return path can have significant impact on the shape and severity of the current waveform delivered to the DUT. Seemingly subtle changes in the test-setup can lead to consequential changes in testing results, leading to repeatability issues. Similarly, seemingly subtle differences between different test-setups can lead to differing testing results between two test facilities, leading to reproducibility issues.


The ESD gun is calibrated to a 2 Ohm (high bandwidth) load. Specifying a single load allows significant deviation/differences between guns— this was a “painful” lesson already learned with HBM test standards. Not only do guns vary significantly, models used for pre-silicon validation vary. A large set of guns/simulation models were evaluated in [9]. From Figure 11, it can be seen that there is a good agreement between a specific model and a specific ESD gun’s waveform for 2 Ohm load.

Figure 11: Model vs waveform for 2 Ohm load

However, the agreement is not good for a 100 Ohm load (Figure 12), which begs the question of whether the gun or the model is more correct. Because the standards do not set an expectation, the question cannot be answered.

Figure 12: Model vs waveform for 100 Ohm load


This article focuses on the specific ESD design challenges, stemming from the fact that all relevant system-level standards were created to validate systems and not components. Applying these standards to individual components requires interpretation, which leads to ambiguity in the meaning of the results. Additionally, there are poorly controlled aspects of the test standards, which can create large variations in the applied stress. Our examples place particular emphasis on the air discharge test and the shortcomings that make it a virtually unreproducible test and, hence, of questionable usefulness.


  1. IEC 61000- 4-2, “Electromagnetic compatibility (EMC), Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test”
  2. ISO 10605, “Road vehicles – Test methods for electrical disturbances from ESD
  3. M. Dekker, T. Smedes, G. Notermans and R. Ashton, “HMM Failure Level Variations Revisited,” 2019 41st Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2019, pp. 1-8, doi: 10.23919/EOS/ESD.2019.8870002.
  4. J2962-1, “Communication Transceivers Qualification Requirements—LIN.”
  5. J2962-2, “Communication Transceivers Qualification Requirements—CAN.”
  6. IEC 62228-1, “Integrated circuits – EMC evaluation of transceivers – Part 1: General conditions and definitions,” 2018.
  7. IEC 62228-2, “EMC evaluation of transceivers – Part 2: LIN transceivers,” 2016.
  8. IEC 62228-3, “Integrated circuits – EMC evaluation of transceivers – Part 3: CAN transceivers,” 2019.
  9. S. Bub, M. Mergens, A. Hardock, S. Holland and A. Hilbrink, “Automotive High-Speed Interfaces: Future Challenges for System-level HV-ESD Protection and First- Time-Right Design,” 2021 43rd Annual EOS/ESD Symposium (EOS/ESD), Tucson, AZ, USA, 2021, pp. 1-10, doi: 10.23919/EOS/ESD52038.2021.9574746.
  10. S. Frei, M. Senghaas, R. Jobava, and W. Kalkner, “The influence of speed of approach and humidity on the intensity of ESD,” in Proc. 13th Int. Zurich Symp. EMC, Zurich, Switzerland, Feb. 1999, pp. 105–110.
  11. M. Ammer, S. Miropolskiy, A. Rupp, F. z. Nieden, M. Sauter and L. Maurer, “Characterizing and Modelling Common Mode Inductors at high Current Levels for System ESD Simulations,” 2019 41st Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2019, pp. 1-7, doi: 10.23919/EOS/ESD.2019.8870005.
  12. N. K. Kranthi, J. di Sarro, R. Sankaralingam, G. Boselli and M. Shrivastava, “Insights into the System-Level IEC ESD Failure in High Voltage DeNMOS-SCR for Automotive Applications,” 2020 42nd Annual EOS/ESD Symposium (EOS/ESD), Reno, NV, USA, 2020, pp. 1-7.

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