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ESD as an EMI Design Problem

Ask a manufacturing engineer how to prevent electrostatic discharge (ESD) problems, and you will hear about ionizers, conductive floors, smocks, wrist straps, and more. Ask an electromagnetic compatibility (EMC) test engineer about ESD, and you will hear about ESD test procedures, test protocols, and more. Ask an EMC design engineer how to prevent ESD problems, and you will hear about transient protectors, ferrites, shielding, and more.

So who is right? All three are correct – but the focus and strategies are different.

The manufacturing engineer emphasizes prevention. When handling sensitive components or circuit boards, even a very small amount of ESD energy can destroy modern electronics. Thus, extreme care must be taken to prevent those events from happening by controlling the environment to prevent ESD events.

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The test engineer emphasizes validation. This is done by following standard test protocols to demonstrate compliance to specified ESD requirements. In many cases these are also legal requirements (i.e., electronic devices imported into the European Union) or contractual requirements (i.e., certain military standards). As a minimum, I recommend using ESD tests as internal engineering requirements, resulting in more robust designs.

The design engineer emphasizes mitigation. Since the environment usually cannot be controlled, the equipment must be hardened to withstand ESD events. Fortunately, sensitive components are not directly exposed to ESD, but are protected by enclosures and extra components that provide circuit protection.

In this article, the focus is on ESD as an EMI design problem. We will first look at ESD through the lens of the classic “source-path-victim” EMC model. Next, I’ll share eight ESD design solutions. Finally, I’ll share some thoughts on ESD testing you can do in the engineering lab to validate your design prior to formal compliance testing.

ESD as an EMI Source

Most ESD events are the result of triboelectric charging, caused by the separation of two non-conductive materials. Examples include a person walking or scuffing shoes, paper moving in a printer or printing press, rubber belts in machinery, and even an integrated circuit sliding in a non-conductive package. The charge separation results in voltage potentials that eventually breaks down in air, resulting in an ESD event.

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A primary concern is human ESD, since humans will likely touch our electronic devices. Although it may take seconds or even minutes to charge a human, the discharge can occur in about a nanosecond, and lasting only a few nanoseconds. A secondary concern is machine ESD, which is much harder to define and is highly system dependent. The peak current from a human can exceed 10 Amps. Not enough energy to harm a person, but more than enough to damage sensitive electronics. Since a one nanosecond discharge has about the same rate of change as a 300 MHz sine wave, we often view ESD as a 300 MHz EMI problem. Very fast, and very nasty!

ESD and EMI Coupling Paths

ESD can attack via two paths – conduction (direct) and electromagnetic radiation (indirect). For many years, conduction was considered the main threat. But with the increasing speed of electronic devices, both must now be considered. Modern ESD test procedures address both paths. The indirect effects are real, and I’ve seen indirect ESD induced failures occur up to 20 feet away.

There are multiple direct conduction paths for ESD too. Circuit inputs/outputs can be upset or damaged by ESD currents and voltages. Power/ground inputs are usually more robust, but upsets can still occur due to power/ground bounce. Push 10 Amps across 0.5 Ohms, and you have a 5 volt bounce.

These multiple paths often mean multiple design fixes. For the direct effects, filters/transient protection are used for vulnerable inputs/outputs, while ferrites or other current limiting are used for power/ground paths. For the indirect effects, high frequency shielding is used.

ESD and EMI Victims

As previously mentioned, ESD can cause both damage and upset. Damage is common when ESD is injected on an unprotected I/O pin – digital, analog, or even power. Upset is common at lower levels for digital circuits, while analog circuits are usually immune to ESD upset due to slow response times.

Circuits vulnerable to ESD damage include I/O or any other lines directly connected to the outside world. Circuits vulnerable to ESD upset include resets, interrupts, and controls. Unwanted resets are very common with ESD — so common that we routinely add protection to these devices. Memory corruption is also common, due to corruption of read/write or memory latch controls.

Even power circuits are vulnerable. Although much less common, I have seen ESD shut down power supplies due to ESD upsetting power protection circuits. In this case, a chain of effects initiated by ESD.

ESD and EMI Design Solutions

When analyzing ESD events, focus on current rather than voltage. An ESD event is like a dam bursting in the mountains. The pressure (voltage) builds, but once the dam breaks, the pressure drops but the rushing water (current) causes the damage. If the rushing water hits another dam, the pressure (voltage) again rises, and the resulting voltage “punches through” and causes the damage. But it is all initially driven by the ESD current.

You have three choices when designing for ESD – prevention, diversion, and limiting.

  • Prevention – Use spatial separation and/or insulation to protect vulnerable electronics.
    The 15 kV ESD can easily jump a centimeter in air, and perhaps more if sharp points concentrate the fields (remember Ben Franklin and the lightning rod.)
  • Diversion – Route current away from a critical circuit node with a transient protector or small capacitor (1-10 nF typical). In the former case, the transient protector must be fast enough for ESD, which means either a silicon protector or a surface mount metal oxide varistor (MOV). Note that discrete MOVs or arc gaps are generally not fast enough for ESD.
  • Limiting – This technique is often used to prevent dumping large ESD currents into the circuit power or grounds. Series ferrites are useful here (100 Ohms @ 100 MHz typical) as they do not cause DC voltage drops. On I/O lines, the ferrites should be placed ahead of any shunt capacitors to limit the currents into ground.

Eight Ways to Prevent ESD/EMI Problems

Here is a checklist of design techniques I’ve used over the years for ESD:

  1. Avoid Static Build-up.
    • Use static dissipative materials if the system has moving plastic or rubber rollers
    • Drain the charge with tinsel (common in printers)
    • Ground all internal metal parts
    • If possible, increase humidity (>50% preferred)
    • Consider wrist straps, dissipative flooring, and/or “touch me” pads
  2. Prevent discharge from occurring
    • Insulated control panels with adequate voltage breakdown protection
    • Watch out for sharp points such as screws which concentrate fields
    • Pay attention to seams – ESD can easily jump through plastic seams
    • Bond switches, controls, and panels to metal enclosures
  3. Use multi-layer boards
    • Power/ground planes greatly reduce impedance and coupling
    • Typically ten times or more immune to ESD, both conducted and radiated
    • For one or two layer boards, assume 20 nH/inch, or up to 200 Volts/inch on a trace
    • Keep ESD currents OFF one or two layer boards
  4. Filter I/O circuits
    • All lines entering or leaving board are vulnerable and must be protected
    • Use filters and/or transient protection, including power and ground
    • Series ferrites preferred on all lines, including power and ground
    • Common mode ferrites useful for high speed digital interfaces
  5. Filter critical circuits on boards
    • Protect reset inputs with 1 nF shunt capacitors
    • For extra protection, add series ferrites (necessary for off board reset buttons)
    • Locate reset controller close to processor
    • Protect other critical control inputs, such as Read/Write
    • Decouple all power and other critical nodes with 1-10 nF capacitors
  6. Use metal connectors and back shells with shielded cables
    • Full circumferential bond of shield to connector
    • Bond chassis connector to chassis
    • Gasket if necessary to seal gaps around connectors
    • Avoid cable “pigtails” like the plague – never terminate a cable shield through a drain wire
    • Very important – cable/connector problems helped put my two kids through college
  7. Proper high frequency shielding
    • Plastic enclosures may block direct ESD but pass radiated ESD
    • Thin conductive materials fine – plating, aluminum, steel
    • Seal seams and penetrations – keep gaps under two inches, much less preferred
    • Many ESD problems can be solved with simple high frequency shielding
  8. Design software to cope with ESD upsets
    • Assume errors will occur, so design for “noise tolerance”
    • Processor – detect and correct, alarm, or provide “graceful recovery”
    • Memory – check sums, error correcting codes
    • I/O – range check, echo, ack/nack protocols, software filter

ESD and EMI Testing to Validate Your Design

As the old saying goes, “It ain’t over until the fat lady sings.” So it is with testing, which is necessary to verify that your design works as intended. The good news is that you don’t need a test lab or wait until the end of the project to do useful ESD testing.

I’m a big believer in pre-compliance testing during the design phase. In fact, the sooner you begin testing, the more time and design flexibility you have to fix any problems. As nasty and unpredictable as ESD can be, it is in your best interest to do so.

You can rent or buy a suitable ESD tester that meets industry specifications. I recommend following the test protocol of EN-61000-4-2 (the European test method) unless you have your own special requirements. This protocol does a very good job of simulating the human ESD discharge, and is widely recognized around the world.

Start with the indirect tests, as they are less likely to cause damage. Once hardened for indirect ESD, continue with the direct tests. A word of caution — the direct tests can cause damage, so be sure you have spare boards or parts.

In both cases, start with a low voltage and increase in 2 kV increments, using both polarities. For ESD is it not adequate to simply test at the highest level. There have been numerous cases of “windows of susceptibility” at interim test levels. These are believed to be due to different slew rates at different test voltages.

Determine your failure criteria and how to observe it. You may need special software to do this, along with special hardware, such as a blinking LED to indicate a “heartbeat.” Best to let the unit under test tell you when it fails, rather than adding external equipment. Keep it simple.

Next, determine how much test time you are willing to discard. For example, if four hours, then run a new baseline every four hours to be sure nothing has changed. Be aware that latent failures are common, particularly when doing the direct ESD tests.

Finally, I recommend testing to the maximum recommended level of 8 kV contact/15 kV air, even if your legal requirement is lower. This is particularly important for North America, where the real world ESD levels are typically higher than in Europe.


In closing, I hope this article has been helpful in addressing ESD as an EMI design problem. As I’m fond of saying about all EMI design problems, an ounce of prevention is often worth a pound of ferrite or shielding.

author_gerke-darylDaryl Gerke (PE) is the surviving partner of Kimmel Gerke Associates, Ltd., an engineering consulting and training firm that specializes in EM/EMC/ESD design issues. The firm has been in full time practice since 1987. 

Daryl and his late business partner, Bill Kimmel (PE) solved hundreds of EMC problems across a wide range of industries (computers, medical, military, vehicular, avionics, telecommunications industrial controls, and more.) They also trained over 10,000 students on EMC design practices through their public and in-house seminars.

Daryl has a BSEE from the University of Nebraska, is a Registered Professional Engineer (PE), and is a NARTE Certified EMC Engineer. He resides in Mesa, Arizona and can be reached at (   

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