Electronic products are designed and tested to a variety of EMC requirements. Although specific requirements and test methods can vary by industry, ESD, transient immunity, RF immunity and RF emissions are evaluated for most products – certainly for all products that require a CE Mark.
In order to assist with meeting EMC requirements, new technologies are emerging to help engineers to both locate and correct EMC problems and to assist in design to insure later compliance. These new technologies include tools to pinpoint areas of potential sensitivity, identify emissions with reasonable correlation to far field measurements, and current visualization techniques to track currents flowing into a circuit. Each will be discussed in the following article.
Background
To simulate the effect of an ESD event during Immunity scanning, a magnetic loop probe is used to subject the DUT to a magnetic field which can then couple into ICs, traces and connecting cables. Before we get into the scanning techniques, it’s important to understand why injecting a magnetic field into a circuit to simulate an ESD or other transient makes sense. Further, also electric fields can be used, for example on an LCD display touch screen and the distributed circuit is often sensitive to rapidly changing E-fields.
An ESD event induces currents into a system via cables or a direct discharge to a system, sub-system, or external module. As these currents travel through various paths magnetic fields are generated, which in turn, develop voltages along the way. Large currents that develop large voltages can cause hard failures – device damage — from which recovery isn’t possible and the fault is easy to find (smoke!); smaller currents produce smaller voltages that cause upset but no damage. The system can typically be re-set, re-booted, or may even have self- recovery routines to bring the system back on-line. And it’s these failures that are hard to predict or troubleshoot. Scanning with E or H fields does the trick.
ESD events can cause currents of more than 50A to flow directly into a port or via a cable, along a chassis or onto a PCB via secondary discharges. Upset of a system can occur either from direct effects — the ESD current flows on a path along a chassis and voltages are developed that can damage components, or from indirect effects where small currents develop fields that in turn, develop small voltages that can cause upset.
As an example of the direct effect of the high ESD current flowing, one needs to remember:
V= L(di/dt)
Where V= the voltage developed, L=inductance of the path and di/dt is the rate of change in the amplitude of the current. ESD events have very fast rising currents that are in the picosecond to nanosecond range, so it doesn’t take much inductance to develop a significant voltage.
An example of V=L(di/dt) effects can be made as follows:
Assume a poor connection between a USB cable shield and chassis, say a 2nH connection inductance. If we also assume a 5kV ESD event having
a current rising to about 20A in 1ns*: V=L(di/dt) = 40V! The 40V spike will appear inside the enclosure and drive a current into a board.
*(IEC values are 1.2ns risetimes at 3.75A/kV; therefore a 5kV discharge would provide a current of 18.75A.)
ESD upset in a system is often the result of small currents producing localized fields that in turn, are generating small voltages. To give you an idea of voltages required to cause upset in a device, some logic threshold voltages are shown in Figure 1.
Figure 1: Logic Threshold Voltages
Logic threshold levels today can be as low as 0.3V. One can see it wouldn’t take much of an ESD event to produce enough voltage to re-set a device if the voltage appeared in the right place.
The basic technology isn’t new: IEC and other standards require testing for upset and when an upset occurs it’s necessary to find out why and fix the problem. Sometimes operator re-set is allowed, but never for critical systems in avionics, automotive applications and certain medical devices.
Engineers have been using probes to inject fields into a circuit in order to locate trouble spots for some time. Historically, these have been large probes with fields covering a wide area. It’s possible to determine an area of a board that is sensitive but difficult to pinpoint the problem device or circuit. Todays crowded circuit boards and physically small components reduce the usefulness of this method significantly.
To get around the size problem, new scanning technologies using very small loops, less than 1mm in diameter, precise positioning and iterative scanning at different levels provides a 3 dimensional display that allows an engineer to not only identify a sensitive component, but also which pins and associated components are involved . Figure 2 is an example of a scan done on a sensitive circuit.
In Figure 2, the source of the disturbance is a pulse induced via a small H-Field loop close to the surface of the board. The resulting voltages and currents are responsible for the device upset. This is, in fact, the mechanism for most ESD caused upsets.
Figure 2: Scan of a sensitive device, colors indicate sensitivity levels, with red being most sensitive (Courtesy of Amber Precision Instruments)
ESD/EMC scanning is done by stimulating a location on a board and observing the system response, taking care to NOT cause circuit damage. An example of an automated system for ESD/EMC scanning is shown in Figure 3.
Figure 3: Algorithm for an automated scanner
Upset is automatically detected by monitoring key functions of the system under test. Optical monitors are used to detect changes in a display, V/I monitors for reset lines, audio detectors for some circuits, data streams, etc… almost any key function can be monitored automatically for testing.
Re-set is also a requirement for automated scanning. When a failure is detected, the system being tested needs to be brought back to a known operating state before testing can continue. This can easily be done for most products using external switching to re-set and/or re-boot a system. More complicated systems may require more complex monitoring, such as re-boot, send an instruction to the system to set it in a known condition and then exercise the system to make sure it’s functional again.
RF Immunity scanning is a useful tool for locating nodes in a circuit that are susceptible to specific frequencies or ranges of frequencies.
This is basically a sub-set of the EMC immunity scanning described in the previous section. The fully automated scanning system shown in Figure 4 is easily adapted to RF immunity scanning; however, there are some differences in required hardware.
Figure 4: Fully Automated ESD/EMC Scanner
An RF immunity scan requires an RF Sweep generator capable of covering the frequency range of interested as well as the necessary amplifiers to drive the probes. In addition, levels need to be automatically adjusted to compensate for the frequency response of the probes. This isn’t difficult and is being done all the time with antennas in large chambers used for RF immunity testing of a full system. Numerous software routines and calibration procedures exist and can easily be modified for use with RF Immunity scanning.
All the RF instrumentation and software required for this test is readily available.
EMI Scanning
The basic scanning system used ESD/EMI Immunity and RF immunity scanning can be used to locate and quantify radiation originating in a circuit. Near-field (NF) EMI scanning is a technique used by several manufacturers to evaluate boards for radiation. This is a useful tool for locating the source of RF radiation and its relative amplitude, but correlation to a far-field (FF) test is difficult. Most EMI scanners provide only NF results, which can be useful, and some scanners use algorithms to estimate the far field but to do it properly and have correlation with FF tests requires having the phase information associated with radiated field.
Maxwell’s equations tell us that knowledge of the near field in magnitude and phase is sufficient to reconstruct a model of the source and obtain the far field emissions. This information significantly improves modeling for RFI analysis, which can be used to predict RFI coupling within a system and in turn, be used to qualify IC’s and modules to reduce the chance of RFI problems later in product design.
Resonance Scanning
Resonances in a circuit increase the coupling from an external field at the frequencies of resonance. This is critical for EMC since increased coupling equals an increased transfer of energy from the external field to a resonant circuit and thereby increases the chances of upset or circuit failure. The amount of coupling enhancement due to resonance depends on the Q of the circuit.
Circuit upset due to RF sources generally occurs at specific frequencies and not over a broad spectrum. If an engineer could determine what resonances exist in a design – location, frequency and Q – steps can be taken to minimize the potential for RF Immunity problems.
Resonance scanning can take it one step further by helping to determine the likelihood of an RF problem in addition to location, frequency and Q. This is done by first doing a resonance scan with the system unpowered to determine location, frequency and Q of a circuit. Since one cannot reasonably test every point at every frequency it is reasonable to only test at those locations and frequencies where resonances were detected. This is a way to reduce the test time for an RF immunity scan significantly.
Once the RF immunity scan at resonant locations is complete, we then have a complete set of information: location, frequency, Q and the relative sensitivity at each location and therefore the likelihood that any resonant location will be a problem.
Current Scanning
Current Scanning is a method of visually re-constructing the current flow on a board caused by a transient event.
Using a well-controlled current source and specially designed probes, it is possible to make measurements over an entire DUT and produce a video that shows how the injected currents flow with a resolution of better than 100ps. This can be extremely useful to determine the performance of protection components and aide in determining where protective devices may need to be located.
In the example of Figure 5, the bulk of the current is diverted through a primary protection device located at the input to a DUT but residual current can be seen traveling toward a semiconductor device that probably has an internal protector. In addition, currents may be observed moving in unexpected directions providing an invaluable tool to the engineers.
Figure 5: Snapshot of injected current through a TVS device and towards a protected IC
Summary
New technologies for EMC can provide significant advantages to design, compliance and test engineers by providing information not previously available: precise location of ESD and RF sensitive circuits and components, emissions data including phase measurements for far field characteristics, the location of resonant structures on a PCB and last but not least, the ability to produce an actual video of transient current flow into a board. The data provided from these new technologies will allow more accurate modeling for the design engineer and the ability to locate and correct problems found in the field and in compliance testing. 
Acknowledgments
Dr. David David Pommerenke
Missouri University of S&T EMC – Laboratory
Jin Min, President
Amber Precision Instruments
Giorgi Muchaidze, System Integration Manager
Amber Precision Instruments
This article has not been reviewed by the ICM Editorial Advisory Board.
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Michael Hopkins Michael has over 30 years experience with EMC and ESD as an independent consultant, an employee of Thermo Fisher Scientific working with the KeyTek product lines, EM Test USA. and Amber Precision Instruments. He has worked closely with manufacturers and laboratories world-wide providing training, applications help, and assistance with the development of interpretation of test standards. He is the author of several papers and articles on ESD and other system level EMC phenomena; and has participated in numerous national and international seminars as author, speaker, and panelist. Michael has served with several committees developing standards for industry including IEC as a former working group convenor, the ESD Association, IEEE, SAE and is a member of the U.S. Technical Advisory Group for EMC for the development and maintenance of basic EMC standards. |
