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EMC Bench Notes: Embedded Processor Characterization and Design Review

Introduction

Let’s use the basic tools and spectrum analyzer setup I described in the last two months and use them to characterize an actual embedded processor board based on the Arduino design. I’ll be using an “OSEPP Bluetooth” board, but you can use anything on hand or similar (Figure 1). The schematic and board layout are available in Reference 1. While most Arduino-based boards use linear regulators, I chose this board from my collection because it includes a DC-DC converter and uses a two-layer design with obvious EMC issues.

Figure 1: Our example unit under test is an Arduino-based single-board embedded processor with Bluetooth.

Characterization

This is a great board to evaluate and characterize for EMC issues. It is a two-layer board with ground fill but no solid return planes. It also includes an onboard DC-DC boost converter with a three-terminal 3.3V linear regulator. The processor is an ATMEGA328P with an external 16 MHz crystal clock. There is no other circuitry on the board other than the Bluetooth module, which we won’t be evaluating.

Figure 2: Probing the DC-DC converter switching currents by coupling the medium-sized H-field loop to the switching inductor, L1.

Let’s make some near field probe measurements; first on the DC-DC converter. This is easy to identify because of the large 22µH inductor at the bottom of the board. We’ll non-invasively couple to the inductor (Reference 2), which is connected to the MAX1676 boost converter. Figure 3 shows the resulting frequency domain plot. Placing the spectrum analyzer in Max Hold mode, we can see a lot of switching energy extending out to 200 MHz. You’ll notice that for each plot, I record the system noise floor (yellow trace). I also placed markers at some of the resonant peaks, which we may use in possible future analyses.

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Figure 3: The resulting plot of the DC-DC converter. Note the broadband energy extends out to 200 MHz. The yellow trace is a record of the system noise floor.

In addition, probing around the processor (Figure 4) reveals a lot of 16 MHz harmonic energy along with the broadband energy from the DC-DC converter (Figure 5).

Figure 4: Using the medium-sized H-field probe to characterize the 16 MHz clock harmonics. These narrow band harmonics extend past 500 MHz.

Note that to confirm these narrow band harmonics are indeed 16 MHz, I have placed markers 3 and 4 on adjacent peaks. Subtracting the two frequencies confirms this.

Figure 5: It is easy to observe the 16 MHz clock harmonics that extend past 500 MHz. The yellow trace is a record of the system noise floor.

Now, let’s clamp our current probe around the DC power input cable (Figure 6). I’ve inserted some “bubble wrap” around the power cable to help isolate it from the metal case of the probe. Here, we observe very strong broadband switching noise with a 16 MHz peak (Figure 7).

Figure 6: Using an RF current probe to measure the high-frequency harmonic currents flowing along the DC power cord.

 

Figure 7: Not only is there the usual broadband EMI due to the DC-DC converter, but we also observe several 16 MHz clock harmonics. These would likely cause radiated emissions. The yellow trace is a record of the system noise floor.

Now that we’ve characterized the high-frequency currents traveling along the power cord, how about measuring the harmonic energy of a wire connected to the system ground return? This would represent an I/O cable, such as a USB, attached to the board (Figure 8).

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Figure 8: We can simulate an I/O cable, such as USB, by connecting a wire to the system ground return and measuring the high-frequency harmonic currents using an RF current probe.

Using a standard paper clip pushed into the “Gnd” socket and connecting a short clip lead, I measured the emissions in Figure 9. Note that we still see the broadband emissions from the DC-DC converter, as well as several 16 MHz harmonics from the processor clock.

Figure 9: The harmonic currents measured on a short wire connected to the PC board ground return. There is a resonance at 128 MHz, the half-wavelength of the power cable, board, and wire combination. The yellow trace is a record of the system noise floor.

Note the interesting broad peak at 128 MHz. This is a half-wave resonance due to the combined length of the power cord, circuit board length, and attached wire. These physical resonances can reduce the margin or even throw you over the limit if not mitigated.

Mitigation Solutions

Let’s find out why this board is so noisy! Looking at the top and bottom layers reveals the main issue, and that is no solid return plane (Figure 10).

Figure 10: Here is the PC board layout showing the top (in red) and bottom (in blue) layers. Because there is no solid ground return layer, the fields from the DC-DC converter and 16 MHz clock couple throughout the board.

Ground fill is a fairly common technique when laying out PC boards, and one of the main reasons is that it conserves the etching chemicals and/or prevents board warpage. However, for EMC reasons, ground fill is debatable as to usefulness and can actually lead to “high-frequency traces crossing gaps” (Reference 3). In the case where we lack a solid return plane, this issue is compounded by the multiple possible couplings between top and bottom layer routing.

Digital signals are not the result of electron flow through circuit traces but are propagated via electromagnetic waves between the circuit trace and the nearest other metal. Because we lack a solid ground return plane, these EM waves must be “trapped” between two pieces of metal at all times to propagate the signal energy from point A to point B. However, without an adjacent and solid return plane, the signal energy in the EM wave will couple to all other traces they pass by. Please refer to my PC board design series starting with Reference 4.

It’s possible to re-lay out this board with the top layer as mainly routed power and signals and then use a semi-solid return plane for the bottom layer with minimal non-critical signal routing. You’d need to be careful to avoid high-frequency traces crossing gaps in this return plane.

Many of my clients have already invested their design in a two-layer board, only to learn at the last minute that it may never pass EMC requirements. So, often, I’ll suggest keeping the current layout but simply adding two additional ground return planes as layers 2 and 3, which should be bonded together (along with all ground fill) with stitching vias in a grid pattern. Today, the cost differential between two- and four-layer boards is insignificant, so this is often the most cost-effective solution. The suggested stack-up is shown in Figure 11.

Figure 11: One possible stack-up suggestion with two added ground return planes that would likely mitigate most all the EMC issues: radiated, conducted and immunity.

Summary

In this exercise, I’ve purposely selected a board design with known design issues to show the basic process I use for characterizing a circuit board using some basic EMC probes. I suspect that adding the two solid ground return planes would resolve most of the emissions and immunity problems.

There are other design issues that would preclude me from using this particular board in a “real” product. For example, it lacks power input filtering as well as filtering or ESD protection on the I/O pins. I’d also change the I/O connectors to include optional I/O cable shields.

In future articles, we’ll be characterizing a more complex embedded computer with USB, Ethernet and HDMI ports, along with multiple DC-DC converters.

References

  1. OSEPP Bluetooth module design information
  2. Wyatt, “Characterize DC-DC converter EMI with near-field probes,” EDN.
  3. Wyatt, “Gaps in return planes – yes or no?” EDN.
  4. Wyatt, “Design PCBs for {low} EMI, Part 1: How signals move,” EDN.

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