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Effectiveness of Multilayer Ceramic Capacitors for Electrostatic Discharge Protection

A simple technique to deal with ESD can be achieved by mounting multilayer ceramic capacitors (MLCC) at the PCB I/O connector pins that is the ESD entry point. EMC engineers recommend using 0603 MLCC’s placed at close proximity to each connector pin, mandating low-inductance mounting strategy associated with the PCB traces and vias. When selecting surface-mount techonology (SMT) MLCC for ESD protection of I/O pins, engineers specify the ESD capacitor value, its DC voltage rating, and a choice of technology (X7R or C0G). MLCC, as an ESD bypass or shunt device, is used to divert the ESD current to ground. ESD protection devices should perform ESD mitigation and should not exhibit degradation, while maintaining ESD robustness throughout the life span of a product. Nevertheless, post-ESD examination of small foot-print 0603 MLCC’s reveals serious structural damage, manifesting itself electrically in a dramatic change in the impedance characteristics. This is a major departure from a pre-ESD capacitor, thus resulting in excessive low frequency leakage and functional misbehavior.


Electrostatic discharge (ESD) is one of the most important reliability problems in the electronic circuit industry. Typically in the integrated circuit (IC) industry, one-third to one-half of all field failures (customer returns) are due to ESD. As ESD damage has become more prevalent in newer technologies due to the higher susceptibility of smaller circuit components, there has been a corresponding increase in efforts to understand ESD failures through modeling and analysis. Manufacturers of integrated circuits provide ESD test information. However, the ESD data on IC level standards (human body model (HBM), charged device model (CDM), machine model (MM) and latch-up-to-the-system testing) is often confusing.

Design of robust ESD circuits remains challenging because ESD failure mechanisms become more acute as critical circuit dimensions continue to shrink. Circuit board designers are further constrained by the ability to design highly congested PCB’s and meet ESD requirements. HBM provides much insight into device behavior during an ESD event [1,2].

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An ESD event is the transfer of energy between two bodies at different electrostatic potentials, either through contact or via an ionized ambient discharge (a spark). This transfer has been modeled in various standard circuit models for testing the compliance of device targets. The models typically use a capacitor charged to a given voltage and then some form of current-limiting resistor (or ambient air condition) to transfer the energy pulse to the target.

In order to meet the module level ESD tests, various methods and techniques on printed circuit boards have been implemented and investigated. One effective technique is to add discrete noise-decoupling components or filters into complex CMOS based IC products to decouple, bypass, or absorb the electrical transient voltage (energy) under the system-level ESD test [3]. Various types of noise filter networks can be employed to improve system-level ESD stress tests, including capacitor filters, ferrite bead, transient voltage suppressor (TVS), metal oxide varistor (MOV), and 2nd order LC filter or 3rd order π-section filters.

Multilayer ceramic capacitors (MLCC) are employed as an ESD bypass mechanism at the connector pins of electronic control modules. An automotive control module may require the use of a single high-density connector with pin density in excess of 200. In a typical application, a connector may present the designer with a matrix of 4 x 50 (4 rows of 50 pins at each row) in a tightly congested PCB real estate. To accommodate the ESD protection for each and every I/O pin at the connector of highly congested PCB real estate, design engineers recommend the use of 0603 style MLC capacitors. In most applications, MLC capacitors used for ESD protection are rated for 100 V stress level. However, post-ESD characteristics of MLCC’s are often ignored or misunderstood. In reality, MLCC’s exposed to ESD stress exhibit a dramatic shift in characteristic impedance behavior. Careful examination of MLCC’s reveals permanent structural damage resulting in excessive low frequency leakage. Post-ESD behavior of MLCC’s results in a functional deviation for the control module, and it is fundamentally unsafe to use the product for its intended application. It is suggested that low profile 0603 capacitors should not be used for ESD protection, as reported in this paper. Alternative solutions can be met by the use of low profile transient voltage suppressors (TVS) or fast metal oxide varistors (MOV). However, 0805 style MLCCs with high value capacitance (> 47 nF) provide a good solution and are safe to be used as an ESD bypass element.

MLCCs used as a protective device or mechanism should consider the voltage, peak power and energy as the key components of an ESD threat. It is thus necessary to fully characterize the amplitude and timing of ESD components. Therefore, protection structure should reduce the voltage, peak power and energy threats by shunting the stress currents away from fragile portions of the microcontrollers and other ICs [4].

To solve ESD problems, MLC capacitors employed as ESD bypass or filter component on printed circuit boards (PCB), must shunt the ESD transient current safely to ground. It is important that MLC capacitors, employed as bypass components, absorb the ESD voltage and current safely and protect the device under test with no degradation. In addition, the MLC capacitor must remain within its parametric tolerance for it to be considered a reliable protection mechanism.

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MLC Capacitor as an ESD Protection Device

Multilayer ceramic capacitors are designed for use where a small physical size with comparatively large electrical capacitance and high insulation resistance is required. The general purpose 0603 (1.6 mm x 0.5 mm) class II, type X7R (-55° C to +125° C) is a popular choice for automotive electronic control module design. Therefore, it is a common practice to apply X7R MLCC’s as an ESD protection component at all I/O pins.

Figure 1 illustrates a horizontal grind of the 0603 MLCC (magnification X 100) with plates spaced at 21 mm apart for a 10 nF, X7R type II capacitor. A higher value capacitor is designed with an increased number of plates. This will result in a narrow dielectric thickness, a possible drawback for high voltage transients. At the present time (May 2012), capacitor values for a type II X7R 0603 (100 V) range from 180 pF to a maximum value of 39 nF. However, the capacitor value range for the same technology but with larger physical size (0805) varies from 220 pF to a maximum value of 120 nF. This can be an important factor if ESD protection capacitor value is determined to exceed the maximum value of 39 nF available in 0603 package.

1205 F3 fig1

Figure 1: Standard 0603 MLCC (magnification x100)


Figure 2 illustrates two different styles of MLCC technology with respect to the design of conductive plates. Capacitor manufacturers recognize the over-voltage stress concern and have provided an ESD-enhanced MLCC product. Close examination of Figure 2 demonstrates the style B MLCC is an ESD-enhanced design.

1205 F3 fig2

Figure 2: ‘Standard’ vs. ‘ESD-enhanced’ 0603 MLCC


Figure 3 illustrates a horizontal grind of an ESD-enhanced MLCC at x100 magnification. Comparison with Figure 1 demonstrates the differences in plate geometry design.

1205 F3 fig3

Figure 3: ESD-enhanced 0603 MLCC


1205 F3 fig4

Figure 4: Improved electrical model of MLC capacitors


Printed circuit board designers with fundamental EMC training are required to ascertain the optimum mounting strategy for ESD capacitors. EMC engineers verify a “Y-connection” topology for all of ESD capacitors at every I/O pin of the connector. MLCC must be placed in close proximity to the I/O pin (< 1cm) with a short trace (< 1cm) to the PCB return plane. In this manner, added PCB parasitic trace inductance and its degradation effect on the effectiveness of the ESD bypass capacitor is minimized. The general concern is to limit the added inductance due to PCB mounting inductance, and thus provide a low-impedance path for ESD current flow to return plane.

Another limitation would be to use the lowest value capacitor available, where it is most effective at higher frequencies. ESD would result in an RF current with a bandwidth in excess of 330 MHz. The choice between a 1 nF and 680 pF would easily be reduced to the latter one. However, ESD HBM consists of a 150 pF capacitance, thus a higher value MLC capacitor is preferred. A voltage divider network is established by the combination of HBM capacitor and MLCC. The voltage developed across a larger value MLCC, would lower the voltage developed across an integrated circuit, as indicated in Equation 1.

1205 F3 eq1       Eq. 1

Therefore, where VMLCC << VESD, it is required that CMLCC >> CHBM.


MLC Capacitor Electrical Model

Several electrical models of capacitors are available in textbooks and RF publications used by the EMC/RF community to describe the electrical behavior of MLC capacitors. A simple series RLC network is commonly used to provide accurate behavior for most applications. However, simple RLC model fails to provide the additional technical insight required for analysis of MLCC’s exposed to ESD pulse. The modified model presented in Figure 1 has additional elements to describe the behavior of MLC capacitors exposed to ESD stress. In fact, the model described here is an accurate electrical description, necessary to account for the various physical attributes found within a capacitor.

  1. L1 is the series parasitic inductance associated with plate connections.
  2. L2 is the equivalent series inductance. It is also known as LESL.
  3. R1 is the equivalent series resistance (also known as RESR) and represents the actual ohmic resistance of the plates. This value is typically very low. It causes a power loss of I2R1. Its contribution to the total dissipation factor is D1 = 1/(ωR1C1).
  4. C1 is the nominal capacitance.
  5. R2, the dielectric loss, is a parallel resistance arising from two phenomena; molecular polarization and interfacial polarization (dielectric absorption). Dielectric loss is a complex phenomenon that can change with frequency in most any manner that is not abrupt. Its contribution to the total dissipation factor can be approximated by D3 ~ 1/(ωR2C2).
  6. C2 is the parallel dielectric absorption capacitor.
  7. R3, the leakage resistance or insulation resistance, is a parallel resistance due to leakage current in the capacitor. This value is typically very high. It causes a power loss of V2/R3. Its contribution to the total dissipation factor is D2 = 1/(ωR3C1).

The impedance characteristics of type II (0603, X7R MLC) capacitors for a 680 pF and 10 nF is illustrated in Figure 5.

1205 F3 fig5

Figure 5: Pre-ESD impedance characteristics


ESD is a high frequency pulse with a rise time of less than one nano second, resulting in spectral content in excess of 330 MHz. Hence, the choice of ESD capacitor is reduced to a smaller value MLCC, as seen in Figure 2. Closer examination of Figure 2 reveals a lower impedance for a 680 pF (1.71 Ω at f = 330 MHz) compared with a 10 nF (3.97 Ω at f = 330 MHz). Another consideration may be the result of capacitive loading of certain I/O signals, i.e., CAN bus, where a limited capacitance can be added to the communication bus.

The requirements of a lower value ESD capacitor, as in the previous paragraph, may suggest the use of the lowest value MLCC available to the industry. In addition, there is a third factor that is outlined in Table 1; R3 (insulation resistance) that may add additional incentive for the use of the lowest value MLCC. However, further insight is required to distinguish the apparent easy choice.

In Table 1, all nominal and parasitic elements for both capacitors are listed as per MLCC supplier A.

1205 F3 table1

Table 1: MLCC 0603 capacitor model components

It is important to note that the insulation resistor R3 is an order of magnitude higher in value for smaller value capacitor (Table 1). As more plates are stacked up to accommodate higher value capacitance in the same physical volume of the 0603-style package, the dielectric thickness is reduced by a factor of 14.7. Therefore, as a consequence of thinner dielectric material between the capacitor plates, the insulation resistor for higher value capacitor is reduced by the same ratio (capacitor ratio: 10 nF/680 pF = 14.7, insulation resistor ratio: 0.1 x 1012 Ω/14.7 x 1012 Ω = 1/147. It is clear that a higher value capacitor will sustain a dielectric breakdown in lower ESD voltages. It was suggested by this argument, for ESD applications, only necessary to consider lower-value capacitors with higher insulation resistance in order to protect for dielectric breakdown, i.e., 680 pF vs. 10 nF. Further investigation was required to address the accuracy of aforementioned statement.

If a smaller capacitor presents a higher insulation resistance as shown above, it is important to examine the behavior of the insulation resistance after ESD tests. For further insight, it is important to evaluate the impact of ESD stress on 680 pF and 10 nF capacitors by characteristic impedance of post-ESD capacitors.

Human Body ESD Test

ESD tests for automotive applications are derived and based on a human body model specified by original equipment manufacturers (OEM) [5,6,7,8,9].

A typical HBM discharge network consists of a 150 pF capacitor with a 2 kΩ resistor. The HBM capacitor can be charged up to 25 kV for an air-discharge test. The static charge accumulated on the 150 pF discharge network capacitor (charged to 25 kV) would amount to 3.75 μC. ESD is a high-frequency, high-voltage and high current event that can deposit 46.875 mJ of energy in the protection device in a relatively short time duration.

HBM provides much insight into device behavior during an ESD event. Although the HBM stress is characterized by a certain charging voltage, VHBM, the 2 kΩ series resistor of the circuit is usually much larger than the impedance of the device under test, so we think of the HBM tester as current sources, with the peak HBM current equal to 12.5 A. (VHBM = 25 kV, air-discharge).

Pre-ESD and Post-ESD Measurements

In order to evaluate the impact of ESD stress on 0603 MLCCs, two different types of tests were performed. Since a populated electronic control module is the intention of a realistic test, it is important to evaluate the impact of ESD stress per OEM ESD test techniques. In another method, a 0603 MLCC network was prepared, as shown in Figure 6, with two short wires (< 1 cm) at each end. Terminal 1 was connected to a ground plane where an ESD gun return wire would normally be connected. The ESD discharge tip was slowly approached to the floating terminal until an air discharge was achieved.

1205 F3 fig6

Figure 6: ESD air-discharge to 0603 MLCC


Pre-ESD and post-ESD characteristics of the 0603 capacitor were recorded using an Agilent 4294A impedance analyzer (40 Hz – 110 MHz) with the help of an Agilent 16034G test fixture.
Capacitors were removed from test PCB or ESD network wires, and mounted inside the 16034G test fixture for impedance characterization.

It was decided to apply an ESD pulse to a fully populated automotive electronic control module as designed with rigorous EMC guidelines. As OEM ESD requirements provides guidelines [7,8,9] for remote I/O access ESD stress tests. An HBM model with discharge network as outlined in section IV was calibrated and ESD voltage levels from +/- 4 kV up to +/- 25 kV were applied in successive order. After each discharge, the MLCC was removed and analyzed on an impedance analyzer as per the previous method.

Figure 7 illustrates the impact of the ESD pulse at +/-15kV level for the 680 pF capacitor.

1205 F3 fig7

Figure 7: Measured pre-ESD and post-ESD (MLCC 680 pF)

Figure 8 illustrates the impact of the ESD pulse at +/-15kV level for a 10 nF capacitor.

1205 F3 fig8

Figure 8: Measured pre-ESD and post-ESD (MLCC 10 nF)


Post-ESD capacitor dielectric damage is illustrated in Figures 9 through 11 (horizontal grind) on a magnification scale of 100. The physical damage to X7R and C0G technologies are shown.

1205 F3 fig9

Figure 9: Dielectric damage for post-ESD MLCC


1205 F3 fig10

Figure 10: Dielectric damage for post-ESD X7R MLCC


1205 F3 fig11

Figure 11: Dielectric damage for post-ESD C0G MLCC


In Figure 12, a modified electrical model represented as per Figure 4, was used to illustrate post-ESD effects on both capacitors. In the electrical model per Table 1, R3 was replaced with a 500 Ω resistor to represent the nominal pre-ESD value provided by MLCC manufactures in Table 1 (14.7 x 1012 Ω).

1205 F3 fig12

Figure 12: Simulated post-ESD impedance characteristics, R3 = 500 Ω

1205 F3 fig13

Figure 13: Post-ESD impedance behavior

It is important to note that the 10 nF capacitor developed severe leakage from 40 Hz up to 20 kHz, and for 680 pF the upper frequency is approximately 200 kHz. The impedance of both capacitors registers a 500 Ω resistive value in the aforementioned frequency range. It is thus concluded that ESD has caused non-recoverable, permanent damage to the MLCCs. Post-ESD behavior suggests physical damage to dielectric material due to metallization of capacitor plates. In reference to Figure 4, it is clear that R3 has shifted from its pre-ESD nominal value as per Table 1 (for 680 pF, R3 = 1.471 x 1012Ω, or for a 10 nF, R3 = 0.1 x 1012Ω to an extremely low value of 500 Ω).

The issue of why the 680 pF MLCC has a 500 Ω leakage up to 200 kHz, whereas 10 nF shows the ill-effect only up to 20 kHz, can be explained as follows: the circuit of Figure 4 simplifies to the parallel of C1 and R3 at low frequencies, and the knee of the impedance curve appears for f ~ 1/2π R3C1. For post-ESD, the 680 pF MLCC is dominated by R3 from DC to ~ 300 kHz, whereas R3 contributes only up to 20 kHz for the 10 nF capacitor. Figure 13 illustrates the post-ESD leakage resistance degradation.

It is clear that smaller size MLCC will suffer extreme leakage to a much higher frequency range. Use of higher value MLCCs is recommended, in contradiction to previous recommendations.

As an extension to exposure of 0603 MLC capacitors to ESD stress, additional ESD tests were performed on modules populated with larger 0805 MLC capacitors. Figure 14 illustrates the impact of +/- 25 kV HBM ESD stress on a 4.7 nF capacitor. It is clear that a 4.7nF 0805 capacitor would fail the ESD requirements. However, extending the capacitor size (value) in an 0805 package to 10 nF results in ESD compliance.

1205 F3 fig14

Figure 14: Measured post-ESD for a 4.7 nF 0805 capacitor



This study is an examination of the physical damage to the 0603 MLC capacitors exposed to ESD transients. It shows that permanent damage to dielectric material resulted for ESD voltages in excess of 15 kV. The use of 0603 MLC capacitors for I/O connector pins, as an ESD bypass mechanism, is not recommended and should be avoided. However, in larger footprints, 0805 MLCCs will meet the ESD stress for 25 kV requirements, provided the capacitor size exceeds 10 nF, and is rated for 100 V applications. A preferred ESD bypass solution would use a low capacitance transient voltage suppressor (TVS, CTVS < 100 pF) or a fast metal oxide varistor (MOV).

However, I/O pin ESD capacitors in the range of 1 nF to 100 nF are often utilized as an input RF filter at the connector pins. The ESD capacitors provide a bypass element for the induced RF currents on the module harness due to impinging electromagnetic fields. Low value TVS capacitance is insufficient to provide the required filter across the 1 MHz – 200 MHz frequency bandwidth. Use of a TVS in parallel with a 0603 capacitor (10 nF – 100 nF) is recommended, where permissible.



  1. Y. Fukuda, et al., “ESD Protection Network Evaluation by HBM and CDM (Charge packaged Method)”, EOS/ESD Symposium Proceedings, pp. 193 – 199, 1986.
  2. Warren Boxleitner, Peter Richman, Geoff Well, “Characterizing the Stress applied to ICs by different ESD Testers”, EOS/ESD Symposium Proceedings, 1990.
  3. Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih, “On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation”, IEEE Transactions on Electromagnetic Compatibility, Vol. 50, No. 1,pp. 13 – 21, 2008.
  4. Warren Boxleitner, “ESD Stress on PCB Mounted ICs Caused by Charged Boards and Personnel”, EOS/ESD Symposium Proceedings, 1990.
  5. ISO10605:2008, Road Vehicles Test Method for Electrical Disturbances from Electrostatic Discharge, February 2008.
  6. IEC61000-4-2, “Electromagnetic Compatibility (EMC) – part 4-2: Testing and Measurement Techniques – Electrostatic Discharge Immunity Test”, EN 61000-4-2:1995, Amendment 1: 1998, Amendment 2:200, 1995.
  7. Ford Motor Company, EMC-CS-2009, September 2009.
  8. General Motors Corporation, GMW3097 Rev. 5, May 2006.
  9. Chrysler/Fiat Group LLC, C S-11979, April 2010.


Cyrous Rostamzadeh
Senior IEEE Member
Senior EMC Technical Specialist,
Robert Bosch LLC, Plymouth, MI, USA

Professor Flavio Canavero
IEEE Fellow
Politcnico di Torino, Italy

Professor Feraydune Kashefi
IEEE Member
Department of Electrical Engineering at Azad University, Shabestar, Iran

Mehdi Darbandi
School of Electrical & Computer Engineering, Tehran University,

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