Differential Mode to Common Mode Conversion on Differential Signal Vias Due to Asymmetric GND Via Configurations

This article investigates the impact of ground vias placed in close proximity to high speed differential signal vias and the resulting differential mode to common mode conversion. The work shows the influence of the distance between ground (GND) vias and differential signal (Diff. SIG.); the effect of the asymmetrical configuration of the GND vias; the impact of the dielectric thickness and the number of transitions between the planes.

Printed circuit boards (PCB) are continuously getting denser, more complex and have the need to meet operating requirements at higher frequencies. In order to deal with the very high speed digital communications, designers are often forced to use differential signaling to achieve acceptable signal integrity. This however has not reduced the need to control the EMI emissions. When high speed differential signals are routed on PCBs, the intention is to make the two parts of the differential pair as balanced as possible to insure low EMC emissions and high immunity to both external and internal noise. It is well known that any small amount of in-pair skew, rise/fall time mismatch, amplitude mismatch or any asymmetry can quickly create significant amounts of common mode noise on the differential signals lines, which then increases the EMI emissions [1]. Asymmetries in the wiring channels of the differential signals can cause differential-to-common mode conversion which can impact EMC emissions and common-to-differential mode conversion which can degrade system immunity to both internal and external noise sources.

These asymmetries extend to any asymmetry near the differential signal path, including differential vias near a ground-reference via. This work studies the mode conversion levels in the differential signal as a function of ground via distance, frequency, return via symmetry, number of reference planes traversed by the vias and the dielectric thickness. Differential mode to common mode (DM-to-CM) conversion can increase EMI emissions by coupling differential signals onto other vias, connector pins, etc. Common mode to differential mode (CM-to-DM) conversion is equal to DM-to-CM and can cause external disturbances (such as ESD) to couple onto a differential signal as differential noise.

Full-wave analysis of entire boards can be very time consuming and often impossible due to the complexity, therefore analyzing simplified board designs can be helpful. Results from simple geometries can provide understanding of the underlying physics and can be used by most signal and power integrity design engineers as quick guidelines throughout the design process.

MODEL DEFINITION IN MULTILAYER VIA TRANSITIONAL TOOL

The cavity resonance approach to simulating effects between planes in PCBs has been demonstrated to be fast and effective [1], [2]. The Multilayer Via Transition Tool (MVTT) [2] was used as the primary simulation tool for this analysis. This tool is based on the cavity resonance approach and assembles each layer in multilayer PCBs to calculate overall results. It will model the power/ground plane cavities as rectangles (well-defined resonant modes) or infinite planes to avoid plane resonances that would limit the general applicability of the results to specific sized PCBs. In this study we have used infinite planes. This allows us to focus on the effects of ground vias without possible confusion from board size resonances. Figure 1 represents a cross sectional view of this model. The frequency range for which the S-parameters are calculated is 0.1GHz to 10GHz. A typical dielectric constant of 4.3 and metallic thickness of 1mil was used. The transfer function obtained between 0.1 GHz to 10 GHz from the MVTT simulations provides the amplitude of the DM-to-CM on the differential signal vias and traces. In all cases, a lower result (higher negative number) is desirable.

Figure 1: Layout of Models (Port 1 and Port 2 are mixed-mode ports)

MODEL SIMULATION AND RESULT ANALYSIS

Case 1: Common Mode conversion for the case of one GND via placed in the vicinity of the Diff. SIG.
As mentioned above, we wish to quantify the mode conversion from the differential signal due to asymmetric ground via configuration. The common mode noise created will exist both in-between planes [3], [4], [5] and on the Diff. SIG. pair itself. The transfer function is obtained from the model shown in Figure 1 and is used as the basis for all the different sets of models that were used for data analysis.

The distance between the signal vias that make up the differential signal is 40 mils along the y-axis. The location of the ground via (GND1) is at a distance r from the origin, and its positioning relative to the y-axis changes from model to model. As the angular positioning between the GND via and the y-axis increases, so does the percentage of symmetry by which we quantify the symmetrical configuration of our model. When the GND via is aligned with the x-axis, we say that for this case we have 100% symmetry.

In Figure 2 the different curves represent different symmetrical configuration cases (i.e. 8% symmetry would be the worst case scenario and 99.7% symmetry would be close to the perfect symmetry scenario). As expected, at higher frequencies there is more mode conversion for all cases than at the lower frequencies. The other thing to notice is that the best of the symmetry configurations also shows the least mode conversion by a significant amount.

Figure 2: Common Mode Conversion (Scd21) for the case of best and worst symmetrical configurations

Common Mode Noise as a function of the distance of the GND vias from the differential signal
Figure 3 shows the effect of ground via distance and the best/worst case symmetry. We can observe that the distance of the ground via influences how much impact symmetry (or lack of symmetry) has on the transfer function.

Figure 3: Mode Conversion for poor and good symmetry for various GND via distances.

Case 2: Common Mode conversion for the case of two GND vias placed in the vicinity of the Diff. SIG.
The plots in Figure 4 represent the simulation data for common mode conversion as a function of frequency and symmetry [5]. The location of the first ground via (GND1) is at a distance r from the origin, but always in line with the y-axis. While the second ground via (GND2) is also at the same distance r from the origin, its positioning relative to GND1 changes from model to model. As the distance between the two GND vias increases, so does the percentage of symmetry, by which we quantify the symmetrical configuration of our model. When both GND vias are aligned with the differential signal along the y-axis, we say that for this case we have 100% symmetry. Amongst the several values that were considered for the distance between GND vias and the Diff. SIG is the 60mils as shown in Figure 4. Common mode noise is highly reduced when the GND vias are close to perfect symmetrical configuration. The effect of the symmetry on the common mode noise as the distance between GND vias and the center of the Diff. SIG varies is shown in Figure 5. In Figure 6 where we are looking at the common mode conversion of just a few frequency points as a function of symmetry percentage. Amounts of mode conversion will vary based on the design requirements, however at 90% symmetry is where the curves show a substantial noise reduction.

Figure 4: The effect of Asymmetry on Common Mode noise on the diff.signal

Figure 5: The effect of Asymmetry on Common Mode noise on the differential signal. Comparing different symmetrical configurations of GND vias when r varies.

Figure 6: Differential to Common Mode conversion (Scd21) is greatly reduced if symmetry percentage is higher than 90%.

Case 3: Mode conversion as a function of the number of GND planes for the case of two GND vias
In this section we have analyzed the mode conversion on the signal via-pair as the number of reference plane cavities traversed by the vias increases (as for thicker PCBs). In Figure 7 we have looked at the best and worst case symmetry cases of the GND vias relative to the Diff. SIG. As the number of planes increases, the Scd21 amplitude starts to converge. In Figure 8 we have shown how the change in Scd21 is affected by asymmetry (worst vs. best case) as the number of reference planes changes. We have picked several frequency points, and have shown the change in Scd21 as a function of the number of planes. At high frequencies, once convergence is reached there is very little variation in the change of Scd21 amplitude as the number of GND planes increases.

Figure 7: The effect of the number of planes on the common mode noise conversion

Figure 8: Common mode noise as a function of the number of planes through which the differential signal transitions

Case 4: The effect of symmetry on Scd21 for various dielectric thicknesses
In order to determine the effect of dielectric thickness, a number of different dielectric thicknesses were analyzed. The amplitude of the Scd21 varied with dielectric thickness, however the total difference between best and worst case symmetry configurations is approximately the same for all the various dielectric thicknesses (Figure 9). As the dielectric thickness increases, the impact of the GND via increases.

Figure 9: There is little to no change in the Scd21 amplitude amongst cases that correspond to different dielectric thicknesses.

CONCLUSION AND FUTURE WORK

This work quantified the amount of mode conversion from differential mode to common mode, as the GND vias are asymmetrically placed near the differential signal vias. As expected, when the asymmetrical ground-reference vias are close to the Diff. SIG. vias the impact on the mode conversion is the greatest. This would seem to imply that the ground-reference vias should be kept far away from the differential vias. This would be true only if the differential vias had no common mode noise on them from other sources. In reality, there will be some amount of common mode noise on the differential signals from PCB effects and/or silicon imbalances, so a ground-reference via in close proximity to the differential vias is required to allow the return current of this common mode noise to remain close to the matching noise current [4], [5]. Therefore, since a ground-reference via placed close to the differential vias is important and since the effect of ground-reference vias asymmetry is significant, the design rule becomes to maintain one or more ground-reference vias close to differential vias but to insure they are placed symmetrically with respect to the differential vias. Design guideline limits can be determined depending on the amplitude of the intentional differential signal and the transfer function.

The amount of mode conversion is not trivial! A ­40 dB mode conversion factor means that a high speed intentional signal with a 1 volt signal could have a common mode noise amplitude of 10 mV. This alone could prove to be enough to cause a system to fail emissions testing if these differential lines are connected to unshielded cables through an I/O connector.

Another important point is the difference in the amount of mode conversion between good symmetry and poor symmetry. Figure 2 shows a 60 dB delta while Figure 4 shows as much as 80 dB difference. This is very significant and can easily make the pass/fail difference in systems with high-speed differential signals.

Future work will include other ground via configurations as well as optimization studies using tools such as genetic algorithms.

REFERENCES

1. Connor, S., B. Archambeault, and M. Mondal. “The Impact of Common Mode Currents on Signal Integrity and EMI in High-Speed Differential Data Links.” IEEE International Symposium on EMC, (August 2008): 1-5.
2. de Paulis, F. , Y. Zhang, and J. Fan. “Signal/Power Integrity Analysis for Multilayer Printed Circuit Boards Using Cascaded S-parameters.” IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 4, (November 2010).
3. Gu, X. , R. Rimolo-Donadio, Z. Yu, F. de Paulis, Y. H. Kwark, M. Cocchini, M.B. Ritter, B. Archambeault, A. Ruehli, J. Fan, and C. Schuster. “Fast Physics-Based Via and Trace Models for Signal and Power Integrity Coanalysis,. DesignCon 2010, Santa Clara, CA, (February 2010).
4. Jaze, A., B. Archambeault, and
5. S. Connor. “EMI Noise Reduction Between Planes Due to a Signal Via with a Ground Via at Various Distances” IEEE International Symposium on Electromagnetic Compatibility (2011).
6. Jaze, A., B. Archambeault, and S. Connor. “Mode Conversion Due to Asymmetric GND Via Configuration.” IEEE International Symposium on Electromagnetic Compatibility (2012).
7. Jaze, A., B. Archambeault, and S. Connor. “Effects of Nearby Ground Vias on High SpeedSingle-ended and Differential Signals.” DesignCon, 2013.

© 2013 IEEE.  Reprinted, with permission, from the 2013 IEEE International Symposium on Electromagnetic Compatibility proceedings.

	Alma Jaze is an EMC Engineer at IBM in Poughkeepsie, NY. She graduated with a Master of Science in Electrical Engineering in 2006. While having already interned with IBM for three years (in Thermo Development and Power Development), upon graduation she became part of the EMC team. She is currently responsible for all EMC input throughout all phases of product design and development for the High-End Servers Division. In the most recent years, she has been involved in research work that focuses in PCB design effects and has a great interest in computational electromagnetics.
	Dr. Bruce Archambeault is an IBM Distinguished Engineer at IBM in Research Triangle Park, NC and an IEEE Fellow. He received his B.S.E.E degree from the University of New Hampshire in 1977 and his M.S.E.E degree from Northeastern University in 1981. He received his Ph. D. from the University of New Hampshire in 1997. His doctoral research was in the area of computational electromagnetics applied to real-world EMC problems. He is the author of the book “PCB Design for Real-World EMI Control” and the lead author of the book titled “EMI/EMC Computational Modeling Handbook”.
	Sam Connor is a Senior Technical Staff Member at IBM and is responsible for the development of EMC and SI analysis tools/applications. Mr. Connor’s current work activities and research interests also include electromagnetic modeling and simulation in support of power distribution and link path design for printed circuit boards. He has co-authored more than 20 papers in computational electromagnetics, mostly applied to decoupling and high-speed signaling issues in PCB designs. He is a Senior Member of the IEEE and is currently the Chair for the TC-9 subcommittee of the IEEE EMC Society.