Common mode currents are in the origin of many typical problems in EMI/EMC and RF electronics. The best way to understand those currents is to visualize them in your scope or spectrum analyzer.
In this month’s column, I will explain one experiment I use to explain in my courses the concept of differential (DM) and common mode (CM) currents in electronics. That is a fundamental topic especially in cables where large loops with CM currents are responsible for many EMI emissions.
The circuit is included in Figure 1, where a digital clock signal CLK with frequency fo and amplitude Vp goes from left PCB to right PCB using two wires.
The source has Z output impedance and it is applied to a resistor load RL with two AWG26 wires (A) and (B). From a theoretical point of view, A wire is the FORWARD path and B wire is the RETURN path. My current using those paths is my Differential Mode (DM) current.
Both clock and load are included in two PCBs, with ground planes, on a metallic surface as in electronic equipment with chassis.
Left board ground plane is connected (always) to the chassis through a short piece of wire (parasitic inductance Ls1). Right board (load) is floating on chassis or grounded using a piece of wire (Ls2) depending of switch SW position.
Two small parasitic capacitances (Cs1 and Cs2) appear between the ground planes and the chassis and are included in the model.
Two current probes measure clock output current i1 (P1) and net current to the left through (A) and (B) wires (P2). Note that probe (P2) encloses both wires so we can measure i2-i1.
From a basic point of view, current i1 will be square wave, with frequency fo and amplitude equal to Vp/RL. If current goes through cable (A), current through cable (B) would be i2=i1; so measurement of (P2) must result icm=i2-i1=0. That is because we use a “RETURN” wire (B).
But return current takes path (B) only if impedance is lower than any other path (that condition depends on frequency, geometry and installation factors). Note that return current can go to chassis through Cs2 (high frequency) and Ls2-SwON (low frequency) paths returning to left board as i3. That is CM current.
A prototype was built around that idea (Figure 2).
The clock signal is HCMOS, with frequency 1.5MHz and rise/fall times around 5ns. Load resistor was measured as 61.2 ohms.
Measurements were done with a Tektronix TDS 640A. An x10 passive probe in channel CH1 was used to measure the clock signal. Two P6021 current probes were used for (P1) and (P2).
Four cases were analyzed (Figure 3).
CASE 1: No return wire (B) and floating (SW off) right board. Vp (CH1) is 5V and, theoretically, i1 (CH2) must be zero (right board floating) but stray capacitances like Cs2 create the spikes (synchronized with CLK dv/dt). You can radiate harmonics of
your clock.
CASE 2: No return wire (B) and right board grounded (SW on). Vp is reduced to 2.5V because RL loading and i1 (CH2) is square wave with amplitude 2.5V/61.3ohms = 40mA. CM current (CH3) is equal to i1 (180 deg) because all current is returned through chassis. The circuit can be working but this is a dangerous situation for both immunity and emissions. I have seen this configuration in some commercial products using one wire configurations (i.e. for power supply) without return wires (return wire is the chassis).
CASE 3: Return wire (B) is used and right board floats (SW off). CM current in CH3 is near zero because all current is returned through i2 (cable B). Some high frequency spikes appear because the parasitic paths.
CASE 4: Return wire (B) is used and right board grounded (SW on). Now, return current has two paths: wire (B) and chassis. Current distribution in those paths (approximately 50% in the example) depends on frequency and parasitics. This is again a dangerous situation as in case 2.
So, as usual, a final advice: i) think you have return currents and ii) check they take the good path to the source.
