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Product Insights: Charged Device Model ESD Testing


The charged device model (CDM) electrostatic discharge (ESD) testing is useful in recreating the potentially destructive discharge mechanisms in automated component handling systems and similar situations where semiconductor devices are packaged and assembled. In these situations, the component becomes highly charged and is then quickly discharged when it encounters a conductive object that is at a lower electrostatic level. This encounter often results in dielectric breakdown and failure of the component. Since this event involves a low-impedance, metal-to-metal transfer of charge, with peak currents reaching tens of amperes within a very short amount of time (within nanoseconds), and there are multiple sources of parasitics involved, it is very difficult to reproduce. Therefore, to increase reproducibility and trust in any semiconductor component manufacturer’s claims of ESD robustness encountered in packaging and handling of their device, a standard (reference 1 is an example) was established to clearly define field-induced CDM ESD test methods for these devices.

Purpose of a Standard CDM ESD Test Method

A standard CDM ESD test method aims to establish a test method that accurately reproduces CDM failures and provides dependable, repeatable CDM ESD test conclusions from tester to tester (equipment to equipment), irrespective of component type or packaging. Accurate classification and comparison of the CDM ESD sensitivity (susceptibility) levels of different semiconductor components is possible by obtaining reliable test data from this standardized CDM test method.

CDM ESD Tester

The normative section of the standard (reference 1) describes the “field-induced” (CDM-FI) CDM test method. One of the informative annexes describes an alternative “direct-contact” (CDM-DC) method. However, the CDM-DC method does not produce results that compare well with results using the hardware and field-induced method specified in the body of the standard, so this CDM test method is not described further in this article.

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VSWR and its Effects on Power Amplifiers

Voltage Standing Wave Ratio results from an impedance mismatch between a source (an amplifier) and a load (test application). This mismatch can influence the performance of the source.

The CDM-FI tester assumes the use of a resistive current probe. A field plate sits at the bottom of the tester, on top of which sits a dielectric layer. The device under test (DUT) is placed on top of the dielectric layer. Connected to the side of the field plate is a charging resistor (nominally 100 MΩ or greater), and this is connected to switch K1, the purpose of which is to switch between charging the field plate using a high-voltage supply and grounding the field plate.

Placed above the field plate is a ground plate with a hole that allows the pogo pin (ground pin) to protrude through it. The pogo pin is connected to the center conductor of 50Ω coaxial cable, the output of which connects to the 50Ω input of an oscilloscope. The standard specifies the pogo pin to ground plane connections as a 1 Ω current path with a minimum bandwidth (BW) of 9 gigahertz (GHz). These two items make up what is called the current-sensing element in the standard. The entire ground plate is connected either to ground or to the field plate through the high-voltage supply, depending on the position of switch, K1.

Waveform Characteristics

Waveform characteristics are specified without additional passive or active devices (such as ferrites) in the probe’s assembly. This requirement may affect compliance of existing CDM-FI testers which might have used components like ferrites to obtain the correct waveforms. If you have a CDM-FI tester built before 2017, consult your CDM ESD tester manufacturer to see if this requirement is an issue.

For exact waveform requirements of the standard, refer to Figure 2 – CDM characteristic waveform and parameters, Table 1 – CDM waveform characteristics for a 1 GHz bandwidth oscilloscope, and Table 2 – CDM waveform characteristics for a high-bandwidth (≥ 6 GHz) oscilloscope).


For anyone building their own CDM-FI tester, the standard cautions about the potential for having too large of parasitics in the charge and discharge paths because having these unwanted resistance inductance-capacitance (RLC) parasitics in the equipment will greatly influence the test results and comparison of these results with those obtained from complaint CDM-FI testers.

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Specifications for Various Elements of the CDM-FI

Exact specifications for each part of the CDM-FI are described in detail in the standard and are not repeated here. This includes exact specifications for the current-sensing element (resistance plus/minus tolerance, frequency response, and maximum roll-off), dimensions of the ground and field plates (plus/minus tolerance, surface flatness), material composition and thickness (plus/minus tolerance) for the dielectric layer, etc.

Common CDM ESD Test Standards

Other CDM ESD test standards often encountered in the industry include JS-002, AEC-Q100-011, AEC-Q101-005, and JESD22-C101. Reference 1 is based on ESDA/JEDEC Joint Standard ANSI/ESDA/JEDEC JS-002, which resulted from merging JESD22-C101 and ANSI/ESD S5.3.1. Reference 1 contains the essential elements from these original CDM ESD standards, and cooperation between ANSI, ESDA, JEDEC, and the IEC took place in creating reference 1.

Qualification and Verification of the CDM-FI Tester

The standard requires periodic tester qualification, waveform records, and waveform verification, i.e., “The CDM tester shall be qualified, re-qualified, and periodically verified….”

Any change to the main elements of the CDM-FI tester (described previously) requires waveform verification. Luckily, the standard provides what waveform capture hardware is required along with the waveform capture setup and procedure. The standard also provides a detailed qualification/requalification procedure that appears easy to follow. The standard states: “Maximum time between requalification tests is one year.” Suppliers of CDM-FI testers may have their own recommendations for requalification that savvy users of the equipment will follow.

Pro Tip: If you have ever been caught in a situation where you potentially have shipped a non-compliant product because you later found out your tester was not producing the correct output waveform (not a fun situation), you will want to develop a process to re-check your CDM-FI tester’s waveform characteristics as often as feasibility justified (perform a cost/benefit and risk analysis to determine your best options).


This article described the basics of CDM ESD testing using the FI method and why it is important to those who produce semiconductor devices. It included the construction of a CMD-FI tester, some of the nuances involved, and proper qualification and verification of its waveform. Hopefully, you find this information useful.

References and Further Reading

  1. IEC 60749-28:2017, Semiconductor devices – Mechanical and climatic test methods – Part 28: Electrostatic discharge (ESD) sensitivity testing – Charged device model (CDM) – device level.

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