# Charged Board Event (CBE)

Q Charged Board Event (CBE) is an electrostatic discharge (ESD) event that can occur on assembled printed circuit boards (PCB) and electromechanic assemblies. CBE is a system level discharge and there are numerous scenarios whereby it may occur. Are there control methods available to detect and prevent CBE discharges?

A: The short answer to this question is yes, there are methods to both detect and control CBE discharges. Unfortunately, it is not always easy to identify or prevent all CBE discharges. Controlling CBE requires monitoring product charging as well as the contact points where the assembly is connected to various equipment and other sub-assemblies. Current ESD protection strategies may not fully mitigate the CBE risks even though the proper ESD controls are in place. The challenge is that even in a properly controlled electrostatic protective area (EPA) electronic boards and electromechanics can get static charges as those are composite of an insulating board, non-ESD sensitive, and the ESD-sensitive components.

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Basically, CBE is like another common device-level ESD event; the charged device model (CDM) event. During a CDM event, the charge stored in a packaged IC discharges upon contact with a conductive object at or near ground potential. During a CBE event, the charge stored by an entire PCB discharges upon contact with a conductive object. Also like the CDM event, CBE can have a very fast rise time of less than 200ps. Thus, CBE can be thought of as an extension of CDM where the PCB is the “device” that stores the charge. The main difference is that the source or target capacitance of the PCB or electromechanics can be significantly higher than with packaged ICs. This makes the CBE event potentially more hazardous to unprotected devices on the board. As a side note, some tend to misunderstand that much higher levels of CDM protection requirement (for example, a few thousand volts), would mitigate the CBE damage. This is far from reality, while CBE has to be appropriately addressed through precautionary assembly methods as described below.

Electrical components may fail in a CBE when a charged PCB discharges to the electrical ground, discharges to another conductive object with a potential difference, or when any charged object discharges into the PCB. In addition, the actual electrical device with a static charge can also be a display component, a power module or any other similar sub-assembly containing electronics and mechanic parts that then contacts the PCB assembly. The charged object can also be a mechanical part, such as a plastic cover with metal structures. This cover assembly may not be ESD sensitive and static charges on it may not pose any immediate risk, but it can discharge into the PCB or other electronic devices during the assembly process. Therefore, it is critical to identify the possible discharge events that can damage IC components in the electronics assembly.

The CBE discharge does not necessarily cause component failure each time it occurs. Typically, ESD damage requires that a major part of the discharge current travels through the ESD sensitive IC. On-board ESD protection components along the discharge path and lossy PCB traces can provide added protection against ESD damage. Finally, PCB ground and power planes are the most conductive surfaces in the PCB and, as such, are the more likely contact points for electrical discharge. In this case, most of the discharge energy spreads along the PCB power and ground layers and single components on the board see only a fraction of the total ESD stress.

There are also certain stages in the assembly process that have significantly higher risk for CBE discharges. Electrical connectors, such as board-to-board connectors and internal RF connections can have high speed data interfaces with limited ESD protection. These interfaces are typically well hidden in the final product and do not require good ESD protection from system design point of view. However, careful ESD-safe practices need to be followed during the manufacturing process before these sensitive components are properly protected. Thus, when connection is made to the exposed board, care must be taken that the connectors are indeed neutral when contacting to the board during manufacture. Product testing and programming steps are additional assembly line processes where CBE risks are high. The first electrical connection between the tester and assembly is intended to neutralize all potential differences. Therefore, the first contact should be made to a ground pin, but this may not always be possible. One such example is antenna port testing where an RF tester may contact the antenna RF ports directly. In addition, testing and programming phases are typically repeated many times during manufacturing. Consequently, there can be an accumulated risk of damage on boards even though the charging event may have a rather minimal probability of occurring.

An effective way to detect and prevent CBE risk is to analyze each new electronic product as it is processed and handled through the assembly area. The key parameters to monitor are electrostatic charges and potentials on conductive product parts as well as electrostatic fields on insulative materials. In addition, it is necessary to identify the steps where electrical connections are contacted during assembly and have direct connections to the ESD sensitive ICs. This requires detailed information of the product design and careful assessment of the assembly process but improves the chances of mitigating the ESD risk.

More detailed information of the CBE event and control methods is available from ESD Association technical report ESD TR25.0-01-16 Charged
Board Event.

References

1. Olney, A., and L.G. Henry. White Paper 2 – CBM ESD. Publ: www.esda.org, 2005.
2. Industry Council on ESD Target Levels. “White Paper 2: A Case for Lowering Component Level CDM ESD Specifications and Requirements,” Revision 2, April 2010, at www.esda.org or JEDEC publication JEP157, “Recommended ESD-CDM Target Levels.”
3. Ming-Dou Ker, “Investigation on Board-Level CDM ESD Issue in IC Products,” IEEE Transactions on Device and Materials Reliability, VOL. 8, NO. 4, 2008.
4. Thompson, W.H. EOS/ESD Symposium. “EOS Damage: Does It Happen on PCBs?” EOS-6, p 22, 1984.
5. Shaw, R.N., and R.D. Enoch. EOS/ESD Symposium. “An Experimental Investigation of ESD Induced Damage to ICs on PCBs.” EOS-7, p 132, 1985.
6. Enoch, R.D., and R.N. Shaw. EOS/ESD Symposium. “An Experimental Validation of the Field Induced ESD Model.” EOS-8, p 224, 1986.
7. ESD TR25.0-01-16 Charged Board Event
8. Paasi, J. ESD Sensitivity of Devices on a Charged Printed Wiring Board. EOS/ESD, p 143, 2003.
9. Olney, A., B. Gifford, J. Guravage, and A. Righter. “Real-World Printed Circuit Board Failures.” EOS/ESD Symposium Proceedings, EOS-25, pp. xxx-xxx, 2003.
10. Pierce, D. “Can Charged Boards Cause IC Failure?” EOS/ESD Technology, February/March 1988.
11. Tamminen P., Viheriäkoski T., “Product Specific ESD Risk Analysis,” Paper 3B.2, EOS/ESD Symposium, 2011.
12. Boxleitner, W. “The ESD Threat to PCB-Mounted ICs.” EOS/ESD Technology, October/November 1991.
13. Lin, D.L. “FCBM – A Field-Induced Charged-Board Model for Electrostatic Discharges.” IEEE Transactions on Industrial Applications, Vol. 29, No. 6, pp 1047-1052, 1993.
14. Smith, D.C., and E. Nakauchi. “ESD Immunity in System Designs, Systems Field Experiences and Effects of PWB Layout.” EOS/ESD Symposium Proceedings, EOS-22, pp 48-53, 2000.
15. Reinvuo T, Tarvainen T., Viheriäkoski T., and Tamminen P., “Ground Discharge Effect to the Sensitive Component in the Charged Board Type of Electrostatic Discharge,” 9th International Symp. on EMC, pp. 766 – 768, 2010.
16. Tamminen P., Viheriäkoski T., Reinvuo T., Sydänheimo L., Ukkonen L, “Field Collapse ESD Event,” Paper 2B.2, EOS/ESD Symposium, 2014.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds  international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

Pasi Tamminen received the M.Sc degree in Electronics Engineering from Oulu University, Finland in 1997 and continued to work for NOKIA Networks for four years with automated production technologies, testing, machine vision, process control and design for manufacturability. In 2001-2005 he was at VTT Technical Research Centre of Finland working with risk management, EMC/ESD and cleanroom control methods. He received the NARTE ESD Engineer certification in 2005. Between 2005 and 2012 Pasi worked for NOKIA Mobile Phones by managing cleanroom technology and ESD/EMC/EMI control & design related projects globally in manufacturing and supported R&D, sourcing, and quality. Between 2014 and 2015 he worked at Microsoft R&D. In parallel, Pasi has worked with IEC and ANSI standardization bodies, done research on electrostatics, EMC/ESD failures, qualification, and control methods at the Tampere University of Technology and received a degree Doctor of Science and Technology in January 2017. Since 2017 he has worked for EDR&Medeso with the main focus on high frequency electromagnetic simulation methods. Phone: +358-505262479; pasi.tamminen@edrmedeso.com

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